8.8. Running Hardware Tests - 2025-12-16

Symmetric Cryptographic Accelerator Hard IP User Guide

Version: 25.3

1. Introduction
1.1. Terminology
1.2. IP Overview
1.2.1. IP Applications
1.3. Release Information
1.4. Device Family Support
1.5. Resource Utilization
2. Interface Overview
2.1. Clock Signals
2.2. Reset Signals
2.3. AXI-ST Interface
2.4. AXI-Lite Interface
3. Parameters
4. Designing with the IP
4.1. Installing and Licensing IP Cores
4.1.1. IP Evaluation Mode
4.2. Specifying the IP Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic Accelerator Hard IP Flow
4.5. Dynamically Disabling the SM4 Capability
4.6. Error Handling
4.6.1. Steps to Record and Report the Received Errors to the Soft Logic
4.6.2. Detected Error Handling
4.6.2.1. Recovering from a Recoverable Error
4.6.2.2. Recovering from an Internal Error
4.6.3. Key RAM ECC Error Handling
4.7. Error Reporting
4.8. Resetting the IP
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
5. Block Description
5.1. Reset Sequencer
5.2. AXI-ST Ready Latency
5.3. AXI Adapter
5.3.1. MAC Packing
5.3.2. Data Last Indicator
5.3.3. Stream and Channel ID Buffering
5.3.4. TKEEP and LAST_SEGMENT Signals Generation
5.3.5. MAC Dropping on Decryption
5.4. Integrity Check Value Comparison
5.5. GCM Padding and Depadding
5.5.1. GCM Padding
5.5.2. GCM Depadding
6. Cryptographic IP Data Profiles
6.1. MAC Security Profile (MACsec)
6.1.1. MACsec Flow
6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec)
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM)
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS)
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers
8. Design Example
8.1. Functional Description
8.2. Crypto VSIP Top Block Descriptions
8.2.1. Clock and Reset
8.2.2. Host Interface
8.3. Test Configurations
8.4. Software Requirements
8.5. Simulation Requirements
8.6. Steps to Generate the Design Example
8.7. Running Simulation Tests
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests
8.8.1. Supported Boards
8.8.2. Steps to Compile the Design Example for Hardware
8.8.3. Steps to Run the Design Example on Hardware
9. Document Revision History for the Symmetric Cryptographic Accelerator Hard IP User Guide

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