5.1. Reset Sequencer - The reset sequencer manages soft and hard IP resets within the Symmetric Cryptographic Accelerator Hard IP through the reset and reset acknowledgment signals. - 2025-12-16

Symmetric Cryptographic Accelerator Hard IP User Guide
Version
25.3
The reset sequencer manages soft and hard IP resets within the Symmetric Cryptographic Accelerator Hard IP through the reset and reset acknowledgment signals.
Figure 10. Reset Sequencer Block Connections
The following flow describes the reset assertion:
  1. The subsystem_cold_rst_n assertion resets the entire Symmetric Cryptographic Accelerator Hard IP. Each of the soft and hard IP blocks observes the reset signal assertion.
  2. The synchronous reset acknowledgment signal (rst_ack) asserts when the reset assertion has propagated through all of the logic.
  3. Each of the soft and hard IP blocks assert a corresponding reset acknowledgement signal back to the Reset Sequencer.
  4. The Reset Sequencer asserts the subsystem_cold_rst_ack_n signal to logic once the block receives the soft and hard IP blocks reset acknowledgement signals.
The following flow describes the reset deassertion:
  1. The subsystem_cold_rst_n signal deassertion triggers the reset deassertion to the entire Symmetric Cryptographic Accelerator Hard IP. Consequently, each of the soft and hard IP blocks observes the reset signal de-assertion.
  2. The synchronous reset acknowledgment signal (rst_ack) deasserts when the reset deassertion propagated through all of the logic.
  3. Each of the soft and hard IP blocks deassert a corresponding reset acknowledgement signal back to the Reset Sequencer.
  4. The Reset Sequencer deasserts the subsystem_cold_rst_ack_n signal to logic once the block receives the soft and hard IP blocks reset acknowledgement signals from the soft and hard IP blocks.
Note: The Symmetric Cryptographic Accelerator Hard IP keeps deasserting the ready signals on the AXI-ST and AXI-Lite interfaces until the AES/SM4 Inline Cryptographic Accelerator is fully out of reset and ready to accept the incoming packets.