5. Block Description - 2025-12-16

Symmetric Cryptographic Accelerator Hard IP User Guide
Version
25.3

The following block diagram shows the interconnections of Symmetric Cryptographic Accelerator Hard IP.

Figure 9. Block Diagram
Table 24.  Block Description
Block Description
AES and SM4 Inline Cryptographic Accelerator (AES and SM4 ICA)

A hardened IP block that performs the data encryption or decryption. This IP block supports the following:

  • AES and SM4 cryptographic algorithms
  • 128 bit, 256 bit, or 512 bit key size, the key size depends on the specified mode. The 512 bit key includes the tweak and data for the AES XTS mode.
  • Single 512-bit data interface
  • MAC Security (MACsec), IP Security (IPsec), Galois/Counter mode (GCM), and XEX-based tweak-code block mode (XTS)-specific profiles. Each profile provides a unique set of cryptographic settings.
  • Interleaved data profiles (with the exception of MACSec and XTS profile interleaving).
Reset Sequencer Resets the sequence within the Symmetric Cryptographic Accelerator Hard IP. The block interfaces with the central soft reset controller and the AES/SM4 Inline Cryptographic Accelerator. For more information, refer to Reset Sequencer .
AXI-ST Ready Latency Available for AXI-ST ingress responder ports only, the AXI-ST ready latency supports 0 to 15 range and is compliant with the AXI specification. For more information, refer to AXI-ST Ready Latency .
AXI-ST Adapter The adapter handles the AXI-ST interface adaptation and performs the packing and unpacking of the AXI-ST tuser bits into the data bus before the request is sent to the AES/SM4 Inline Cryptographic Accelerator.
ICV Comparison and MAC packing The IP generates an authentication tag and compares it with the authentication tag carried from the decryption process. For more information, refer to Integrity Check Value Comparison .