6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern - This section describes the XTS-specific input and output signals. - 2026-02-24

Symmetric Cryptographic Accelerator Hard IP User Guide
Version
25.3
This section describes the XTS-specific input and output signals.
Table 43.  Generic XTS Profile Pattern Interface Signals
Signal Name Direction Description
algorithm_type Input/Output Indicates the cryptographic operation mode for the corresponding cycle.
  • 0: AES
  • 1: SM4
encrypt_decrypt Input/Output Indicates the type of cryptographic operation for the corresponding cycle.
  • 0: Encrypt
  • 1: Decrypt
key_128b_256b Input/Output Indicates the key size. The signal is only valid when the key_en signal is set to 1.
  • 0: 128 bit key
  • 1: 256 bit key
Note: The SM4 algorithm only supports 128 bit key size.
pattern[2:0] Input/Output
Pattern ID: Indicates the pattern profile selected for the current clock cycle.
  • 3'b100 = GENERIC_XTS: Generic XTS profile
When the signal switches from the IDLE state to the GENERIC_XTS state, indicates that the data associated in the given clock cycle is related to the generic XTS.
TID[9:0] Input/Output Channel ID.

When pattern ID is set to generic XTS, the channel ID indicates to the logic which cryptographic channel or slot the data in this clock is associated with.
key_en Input When set and pattern[2:0] is set to the generic GCM profile, indicates that the data field contains keys to program in the key slots identified by TID[9:0]. You must set the key_128b_256b signal to specify the key size, 128 or 256 bit key.
  • If key_128b_256b = 0:
    • data[127:0] = data key
    • data[255:128] = padded with 0's
    • data[383:256] = tweak key
    • data[511:384] = padded with 0's
  • If key_128b_256b = 1:
    • data[127:0] = data key
    • data[255:128] = tweak key
    • data[511:256] = padded with 0's

This key_en is a standalone operation per clock. You can select to send the keys at one time or individually.

Asserting this signal while data is in process is not allowed.
data_en Input/Output When pattern[3:0] is set to the generic GCM profile, after one clock of key_en, the data_en indicates the rest of the AAD/Data till it reaches the corresponding lengths (Bypass data and AAD). The plaintext data or ciphertext data then follows until assertion of the data_last signal.
MAC_IV_tweak_en   When key_en is set and MAC_IV_Tweak_en is de-asserted, the logic assumes that the you intend to only program the key slot and not program the IV to start a new AES operation using that key.

When key_en is de-asserted and MAC_IV_Tweak_en is set, indicates the start of a new GCM stream using the IV associated with this cycle and using an existing key was programmed earlier into the key slot associated with this channel.
tlast Input/Output When set, indicates that the data ends (EOP) in the current clock cycle.
Note: The tkeep signal specifies the number of valid bytes in this cycle.
Figure 26. Generic XTS Profile: Input Signals
Figure 27. Generic XTS Profile: Output Signals