1.2. Generating the Design - 2025-12-16

F-Tile Dynamic Reconfiguration Design Example User Guide
Version
24.3
Figure 2. Procedure
Follow these steps to generate a design example:
  1. In the IP Catalog, locate and select F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. The New IP Variation window appears.
  2. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named as <your_ip>.ip.
  3. On the IP tab, specify the parameters for your IP core variation.
  4. On the Example Design tab, under Available Example Design, select the Protocol and Base Variant.
  5. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  6. On the Example Design tab, under Generated HDL Format, select Verilog HDL.
  7. On the Example Design tab, under Target Development Kit, select the Board.
    • If NONE is selected, the device OPN of the generated example design is your device selection while creating the Quartus® Prime project.
    • If Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA is selected, the device OPN of the generated example design is AGIB027R31B1E2V. You can expect that the VID settings for LTC SmartVID device are correct.
    • If Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB is selected, the device OPN of the generated example design is AGIB027R31B1E1VAA. You can expect that the VID settings for an Enpirion SmartVID device are correct.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.

    If you want to modify the design example directory path or name from the default value (dr_f_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).