| Parameters | Value | Description |
|---|---|---|
| Select Protocol/mode |
Ethernet to CPRI |
Select the IP protocol for dynamic reconfiguration. |
| Select Base Variant |
25G-1 25G-1 (with 1GE)25G-1 PTP (with 1GE PTP) |
Select the configuration of base variant for dynamic reconfiguration. |
| Example Design Files | Simulation Synthesis |
Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example. |
| Generated File Format | Verilog VHDL |
Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator. |
| Target Development Kit | None Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB |
Target development kit option specifies the target development kit used to generate the project. |
| Auto-Negotiation and Link Training Options | ||
| Enable auto-negotiation and link training |
On Off |
Enables auto-negotiation and link training for the Ethernet port. When the design example is generated using dynamic reconfiguration with AN/LT IP enabled, the design example automatically instantiates the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP. |
| Enable auto-negotiation and link training optimized simulation |
On Off |
When enabled, reduces the simulation time as much as possible while still maintaining the basic AN/LT protocol and be able to send and receive Ethernet frames. |
| Device Initialization Clock | ||
| Select Clock | None OSC_CLK_1_25MHZ OSC_CLK_1_100MHZ OSC_CLK_1_125MHZ |
Selects the proper frequency of the OSC_CLK_1 pin on the device in order to match what is provided on the targeted board. |
Figure 6. Ethernet to CPRI Example Design Tab