3.1. Ethernet Multirate Design Example: Functional Description - 2025-12-16

F-Tile Dynamic Reconfiguration Design Example User Guide

Version: 24.3

1. Quick Start Guide
1.1. Hardware and Software Requirements
1.2. Generating the Design
1.2.1. CPRI Multirate Design Example Parameters
1.2.2. Ethernet Multirate Design Example Parameters
1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
1.2.4. Ethernet to CPRI Design Example Parameters
1.3. Directory Structure
1.4. Compiling the Compilation-Only Project
1.5. Simulating the Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
2. Detailed Description for CPRI Multirate Design Example
2.1. CPRI Multirate Design Example: Functional Description
2.1.1. CPRI Multirate Design Example: Simulation Testbench
2.1.2. CPRI Multirate Hardware Design Example
2.1.3. CPRI Multirate Design Example: Reset Scheme
2.2. CPRI Multirate Design Example: Registers
3. Detailed Description for Ethernet Multirate Design Example
3.1. Ethernet Multirate Design Example: Functional Description
3.1.1. Ethernet Multirate Design Example: Simulation Testbench
3.1.2. Ethernet Multirate Hardware Design Example
3.1.3. Ethernet Multirate Design Example: Reset Scheme
3.2. Ethernet Multirate Design Example: Registers
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic
4.1.1.1. Interfaces
4.1.1.2. Theory of Operation
4.1.1.3. Using Main.cpp file in User Logic
4.1.1.4. User Logic Modes
4.1.1.5. Hardware Testing in Suspend Mode
4.1.1.6. Simulation Testing in Suspend Mode
4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench
5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
6. Detailed Description for Ethernet to CPRI Design Example
6.1. Ethernet to CPRI Design Example: Functional Description
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
6.2. Ethernet to CPRI Design Example: Registers
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

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