1.2.1. CPRI Multirate Design Example Parameters - 2025-12-16

F-Tile Dynamic Reconfiguration Design Example User Guide
Version
24.3
Figure 3. CPRI Multirate Example Design Tab
Table 2.  CPRI Multirate Design Example Parameters
Parameters Value Description
Select Protocol/mode CPRI Select the IP protocol for dynamic reconfiguration.
Select Base Variant 24G CPRI RS-FEC Select the configuration of base variant for dynamic reconfiguration.
Example Design Files Simulation

Synthesis

 Simulation option generates the testbench and compilation-only project. Synthesis option generates the hardware design example.
Generated File Format Verilog

VHDL

 Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator.
Target Development Kit None

Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA

Agilex™ 7 I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB

 Specify the target development kit for the hardware example design. This option is only available if you select the Synthesis option.
Device Initialization Clock
Select Clock None

OSC_CLK_1_25MHZ

OSC_CLK_1_100MHZ

OSC_CLK_1_125MHZ

Selects the proper frequency of the OSC_CLK_1 pin on the device in order to match what is provided on the targeted board.