F-Tile CPRI PHY Multirate IP User Guide - This document describes the features, functionality, and implementation of the F-Tile CPRI PHY Multirate IP Core. - 2025-01-13

Version: 24.3

1. Introduction
1.1. IP Core Overview
1.2. Release Information
1.3. Device Family Support
1.4. Device Speed Grade Support
1.5. Related Documentation
2. Interface Overview
2.1. Clock Signals
2.1.1. Required Clock Frequencies
2.2. Reset Signals
2.3. TX MII Interface (64b/66b)
2.4. RX MII Interface (64b/66b)
2.5. Status Interface for 64b/66b Line Rate
2.6. TX Interface (8b/10b)
2.7. RX Interface (8b/10b)
2.8. Status Interface for 8b/10b Line Rate
2.9. TX Tunnel Interface
2.10. Using TX Tunnel Interface
2.11. RX Tunnel Interface
2.12. Using RX Tunnel Interface
2.13. Status Interface for Tunnel Line Rate
2.14. Serial Interface
2.15. CPRI PHY Reconfiguration Interface
2.16. Datapath Avalon Memory-Mapped Interface
2.17. PMA Avalon Memory-Mapped Interface
3. Parameters
3.1. Analog Parameters for F-Tile IPs
3.2. Sub Profile Parameters Validation
3.3. Adaptation Parameters
4. Designing with the IP Core
4.1. Installing and Licensing Intel FPGA IP Cores
4.1.1. Intel FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options
4.2.1. Reference and System PLL Clock for your IP Design
4.3. Generated File Structure
4.4. Dynamic Reconfiguration Settings
5. Block Description
5.1. Latency Measurement
5.1.1. Deterministic Latency
5.1.2. Calculation for 64b/66b Datapath
5.2. CDR Clock Output
5.3. RX PMA Adaptation
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel FPGA IP User Guide

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