2. Design Example Detailed Description - 2025-12-16

F-Tile SDI II Intel FPGA IP Design Example User Guide
Version
24.2
Product Type
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
ft:sourceName
DITA
The SDI II Intel® FPGA IP core includes the following design examples for Agilex™ 7 F-Tile devices.
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback
Note: The Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol.