2.4.2. HDMI Intel FPGA IP Design Example Parameters - 2025-12-16

F-Tile HDMI IP Design Example User Guide
Version
24.3
Table 11.   Design Example Parameters for Agilex™ 7 Devices
Parameter Value Description
Available Design Example
Select Design Agilex 7 HDMI RX-TX Retransmit with clocked video interface Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.
Select Daughter Card Revision

0: Revision 9

2: No Daughter Card

 Select available HDMI daughter card for Design Example generation.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Note: Design example simulation is not supported if Include I2C is selected.
Synthesis On, Off Turn on this option to generate the necessary files for Quartus® Prime compilation and hardware demonstration.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board No Development Kit, Agilex™ 7 I-Series SoC FPGA Development Kit FA, Agilex™ 7 I-Series SoC FPGA Development Kit FB, Custom Development Kit Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Agilex™ 7 I-Series SoC FPGA Development Kit FA: This option automatically selects the project's target device to match the device on this development kit (AGIB027R31B1E1V).
  • Agilex™ 7 I-Series SoC FPGA Development Kit FB: This option automatically selects the project's target device to match the device on this development kit (AGIB027R31B1E1VAA).
  • Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Note: For Agilex™ 7 I-Series SoC FPGA Development Kit FA and Agilex™ 7 I-Series SoC FPGA Development Kit FB, you may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.