3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) - 2025-12-16

F-Tile HDMI IP Design Example User Guide

Version: 24.3

1. HDMI Intel FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
1.1. Directory Structure
1.2. Generating the Design
1.3. Simulating the Design
1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters
2.4.1. IP Parameters
2.4.2. HDMI Intel FPGA IP Design Example Parameters
2.5. Design Components
2.5.1. HDMI TX Components
2.5.1.1. TX PHY Adapter
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components
2.5.2.1. RX PHY Adapter
2.5.3. Top-Level Common Blocks
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
2.11.1. Software Debug Message
2.11.2. SCDC Information from Sink Connected to TX
2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
3.1. Design Features
3.2. Hardware and Software Requirements
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer)
3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.3.3. HDMI 2.1 RX-Only Retransmit Design Block Diagram
3.3.4. HDMI 2.1 TX-Only Retransmit Design Block Diagram
3.4. Design Parameters
3.4.1. IP Parameters
3.4.2. Design Example Parameters
3.5. Design Components
3.6. Design Software Flow
3.6.1. Configure Redriver Setting
3.6.2. Initialize TX Path
3.6.3. Initialize RX Path
3.6.4. Initialize HDMI TX Register
3.6.5. Wait for RX Path Ready
3.6.6. TX Reconfiguration and Link Training
3.6.7. Set TX Video Clock
3.6.8. Set AXI2CV Configuration
3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
3.8. Interface Signals
3.8.1. Platform Design System
3.9. Hardware Setup
3.9.1. Supporting Additional Video Resolutions
3.9.2. Running the TX-Only Design
3.9.3. Running the RX-Only Design
3.10. Design Limitation (AXI/CV)
4. Document Revision History for the F-Tile HDMI Intel FPGA IP Design Example User Guide

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