Use this feature to check the frequency for the different clocks.
- In the hdmi_rx_top and hdmi_tx_top files, uncomment //`define DEBUG_EN 1.
- Add the refclock_measure signal from each mr_rate_detect instance to the Signal Tap Logic Analyzer to get the clock frequency of each clock (in 10 ms duration).
- Compile the design with Signal Tap Logic Analyzer.
- Program the SOF file and run the Signal Tap Logic Analyzer.
| Module | mr_rate_detect Instance | Clock to be Measured |
|---|---|---|
| hdmi_rx_top | rx_pll_tmds | RX CDR reference clock 0 |
| rx_clk0_freq | RX transceiver clock out from channel 0 | |
| rx_vid_clk_freq | RX video clock | |
| rx_frl_clk_freq | RX FRL clock | |
| rx_hsync_freq | Hsync frequency of the received video frame | |
| hdmi_tx_top | tx_clk0_freq | TX transceiver clock out from channel 0 |
| vid_clk_freq | TX video clock | |
| frl_clk_freq | TX FRL clock | |
| tx_hsync_freq | Hsync frequency of the video frame to be transmitted |