1.4. Simulating the Design - The DisplayPort IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench. The testbench will stimulate rates up to and including the maximum rate selected in the IP GUI.

The DisplayPort IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench. The testbench will stimulate rates up to and including the maximum rate selected in the IP GUI.

Figure 4. Design Simulation Flow

Navigate to the simulation folder of your choice.
Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
Analyze the results.

Table 2. Steps to Run Simulation
Simulator	Working Directory	Instructions
Riviera-PRO*	/simulation/aldec	In the command line, type vsim -c -do aldec.do
ModelSim*	/simulation/mentor	In the command line, type vsim -c -do mentor.do
Xcelium	/simulation/xcelium	In the command line, type source xcelium.sh
VCS	/simulation/synopsys/vcs	In the command line, type source vcs_sim.sh
VCS MX	/simulation/synopsys/vcsmx	In the command line, type source vcsmx_sim.sh

A successful simulation ends with the following message:

# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# Pass: Test Completed