| 2025.12.01 |
25.3 |
20.1.0 |
- Added the DSC Support chapter.
- Added the Simulating the Design section.
- Added the Simulation Testbench section.
- Updated to include Parretto Tentiva DP2.0
Rev 1 support.
- Updated the Hardware and Software Requirements
section.
- Updated the Generating the Design section.
- Updated the DisplayPort IP Design Examples
section.
- Updated the Agilex 7 F-Tile DisplayPort SST TX-only
Design Features section.
- Updated the Simulating the Design section.
- Updated Table: DisplayPort IP
Design Example Parameters for
Agilex™ 7 F-Tile Devices.
- Updated Table: Clocking Scheme Signals.
- Updated Table: Top-Level Signals.
- Updated Figure: Directory Structure.
- Minor text edits.
|
| 2024.06.06 |
24.1 |
20.0.1 |
- Corrected Native PHY to Direct PHY.
- Added values to Top-Level Parameters.
|
| 2024.04.09 |
24.1 |
20.0.1 |
- Updated mentions of
Nios® II to
Nios® V (where
applicable).
- Added a note about obtaining
Nios® V evaluation license in
the Generating the Design
topic.
|
| 2023.11.03 |
23.3 |
20.0.1 |
- Added DisplayPort
RX-only and DisplayPort
TX-only to the list of available design
examples.
- Added the following chapters:
-
Agilex™ 7 F-Tile
DisplayPort SST TX-only Design
Features
-
Agilex™ 7 F-Tile
DisplayPort SST RX-only Design
Features
- Added
Agilex™ 7 I-Series SoC
Development Kit FA and
Agilex™ 7
I-Series SoC Development Kit FB to the list of
boards.
- Updated the link for customers to access
HDCP feature.
|
| 2023.04.18 |
23.1 |
20.0.1 |
- Updated the product family name to "Intel
Agilex 7."
- Added the following new topics:
-
HDCP Over
DisplayPort Design Example for
Agilex™ 7 Devices
-
Translating
DisplayPort Link Training AUX
Transactions
|
| 2022.10.21 |
22.3 |
20.0.1 |
Enabled DisplayPort 2.0 UHBR10
data rate in design examples. |
| 2022.09.02 |
22.2 |
20.0.1 |
- Changed document title from DisplayPort Intel Agilex F-Tile FPGA IP
Design Example User Guide to F-Tile DisplayPort Intel FPGA IP Design
Example User Guide.
- Enabled AXIS Video Design Example
variant.
- Removed Static Rate design and replaced it
with Multi Rate Design Example.
- Removed the note in the DisplayPort Intel FPGA IP Design
Example Quick Start Guide that says Intel Quartus
Prime 21.4 software version only supports Preliminary Design
Examples.
- Replaced the Directory Structure figure with the correct
figure.
- Added a section Regenerating ELF File under Compiling and Testing the
Design.
- Updated the Hardware
and Software Requirements section to include
additional hardware requirements.
|
| 2021.12.13 |
21.4 |
20.0.0 |
Initial release. |