AN 942: Signal Tap Tutorial with Design Block Reuse for Agilex™ 7 F-Series FPGA Development Board - This application note demonstrates how to incorporate internal signal verification into design block reuse flows in the Quartus Prime Pro Edition software. - 2021-12-10
- Version
- 21.3
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Agilex Families
- Device Families > Agilex Families > Agilex 7 > F-Series
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software
- Device Families > Agilex Families > Agilex 7
- Resource Type
- Documentation > Application Notes
- Source Name
- DITA