5.1. Reset Initialization - The F-Tile JESD204C base core and transport layer require various resets for the IP and transceiver. All the resets in the core assert asynchronously and deassert synchronously.

The F-Tile JESD204C base core and transport layer require various resets for the IP and transceiver. All the resets in the core assert asynchronously and deassert synchronously.

Table 15. F-Tile JESD204C IP Resets
Reset Signal	Clock Domain	Description
`j204c_tx_rst_n` `j204c_rx_rst_n`	Asynchronous	Assertion of these signals resets all logic in the IP (MAC, TL, FIFOs).
`j204c_tx_avs_rst_n` `j204c_rx_avs_rst_n`	TX/RX Avalon^® memory-mapped reset for CSR (`j204c_tx_avs_clk`/`j204c_rx_avs_clk`)	This reset is for the Avalon^® memory-mapped slave interface, which consists of the Configuration and Status Register (CSR) blocks. After this reset deasserts, configuration phase starts. You can program the CSR register values if a non-default value is required.
`j204c_tx_rst_ack_n` `j204c_rx_rst_ack_n`	Asynchronous	These signals acknowledge the state of `j204c_tx_rst_n` and `j204c_rx_rst_n`. The reset sequence completion is indicated by the assertion of these signals.
`reconfig_xcvr_reset`	Asynchronous	Transceiver reconfiguration clock. Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins. Intel recommends that you tie this signal to `tx_avs_rst_n`.

5.1. Reset Initialization - The F-Tile JESD204C base core and transport layer require various resets for the IP and transceiver. All the resets in the core assert asynchronously and deassert synchronously. - 2025-12-16

F-Tile JESD204C IP User Guide