The F-Tile JESD204C IP implements
a simple synchronous clear to all data and control logics during link
reinitialization.
Link reinitialization occurs in two ways:
- You manually trigger link reinitialization by setting the link_reinit bit. The hardware clears the link_reinit and reinit_in_prog bits when link reinitialization completes.
- The hardware automatically triggers link reinitialization because of errors. You have full control, through the tx_err and rx_err registers, to set the specific type of errors to trigger link reinitialization automatically. The hardware clears the reinit_in_prog bit when link reinitialization completes.
Note: Link reinitialization does not initiate
SYSREF re-detection. Use the sysref_singledet bit to re-detect SYSREF edge.
Link reinitialization affects only the transport layer and link layer; the CSR, transceiver,
and the PHY-related logics are not affected.