The F-Tile JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.
| Clock Signal | Formula | Description |
|---|---|---|
|
TX/RX device clock j204c_pll_refclk |
PLL selection | The PLL reference clock used by the TX Transceiver PLL or RX CDR. This is also the recommended reference clock to the Core PLL. |
|
TX/RX link clock j204c_txlink_clk j204c_rxlink_clk |
Line rate/66 | The timing reference for the F-Tile JESD204C IP. The link clock is line rate divided by 66 because the link clock operates in a 66-bit data bus domain architecture after 64B/66B encoding. |
|
TX/RX frame clock j204c_txframe_clk j204c_rxframe_clk |
(Link clock frequency*FCLK_MULP) MHz | The frame clock as per the JESD204C specification. The frame clock is always 1x or 2x of the link clock. |
|
TX/RX Avalon® memory-mapped clock j204c_tx_avs_clk j204c_rx_avs_clk |
— | The configuration clock for the F-Tile JESD204C IP control and status registers through the Avalon® memory-mapped interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75 to 125 MHz. |
|
TX PHY clock j204c_phy_clk |
Line rate/64 |
The PHY clock internally generated from the transceiver parallel clock for the TX path. |
| Transceiver reconfiguration clock reconfig_xcvr_clk |
— | The transceiver reconfiguration clock. The frequency range of this clock is 100 MHz – 250 MHz. |
| System PLL clock sysclk |
System PLL clock frequency >= Native clock frequency | The F-Tile system PLL clock frequency is user-defined. The system PLL clock frequency is greater or equal to the native clock frequency. |