2.3.2. Directory Structure - The F-Tile JESD204C design example directories contain generated files for the design examples.

The F-Tile JESD204C design example directories contain generated files for the design examples.

Figure 3. Directory Structure for F-Tile JESD204C Intel Agilex^® 7 Design Example

Table 7. Directory Files
Folders	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f_tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c_f_se_outbuf_1bit.ip
simulation/models	tb_top.sv
simulation/mentor	modelsim_sim.tcl tb_top_waveform.do
simulation/synopsys	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do
simulation/xcelium	xcelium_sim.sh tb_top_wave.tcl
simulation/aldec	riviera_sim.tcl tb_top_waveform.do
simulation/setup_scripts/common	modelsim_files.tcl vcs_files.tcl vcsmx_files.tcl xcelium_files.tcl
simulation/setup_scripts/mentor	msim_setup.tcl
simulation/setup_scripts/synopsys	vcs vcs_setup.sh vcsmx vcsmx_setup.sh synopsys_sim.setup
simulation/setup_scripts/xcelium	xcelium_setup.sh cds.lib hdl.var <cds_libs folder>
simulation/setup_scripts/aldec	rivierapro_setup.tcl

2.3.2. Directory Structure - The F-Tile JESD204C design example directories contain generated files for the design examples. - 2025-12-16