2.2. Step 2: Preparing the Base Revision - To prepare the base revision, extend the debug fabric to the PR regions that you want to debug. - 2025-12-16

AN 841: Signal Tap Tutorial for Stratix 10 Partial Reconfiguration Design
Version
21.3
To prepare the base revision, extend the debug fabric to the PR regions that you want to debug.
To extend the debug fabric to the PR regions that you want to debug:
  1. Instantiate the SLD JTAG Bridge Agent in the static region
  2. Instantiate the SLD JTAG Bridge Host in the default persona of the PR region
For the debug logic to be function properly after partial reconfiguration, the design needs a reset signal. To add a reset signal to the design:
  1. Instantiate the Reset Release Intel FPGA IP in the static region
  2. Instantiate the Intel Configuration Reset Release Endpoint to Debug Logic IP in the PR region.
The Reset Release Intel FPGA IP generates the reset signal for the Configuration Reset Release Endpoint to Debug Logic IP.