F-tile Architecture and PMA and FEC Direct PHY IP User Guide - Describes architecture and implementation details for the Intel Agilex® 7 F-tile physical (PHY) layer IP, PLLs, and clock networks. Refer to these chapters for IP instantiation, connection, simulation, and tile placement for Intel Agilex® 7 F-tile designs. F-tile has up to 20 PMAs per tile, each with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications. F-tile contains hard IP for PCI Express* * ( PCIe* *) and Ethernet applications. - 2023-09-07

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23.2-4.5.0