E-Tile Hard IP Agilex™ 7 Design Example User Guide Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration - Describes the design example variants of the E-Tile Ethernet Hard IP for Agilex 7 FPGA and E-Tile CPRI PHY for Agilex 7 devices. These design example variants generates the necessary files to simulate and compile the designs. - 2025-02-21
Version
24.3.1
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example
2.1. Quick Start Guide
2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex™ 7 FPGA Design Example Testbench
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Agilex™ 7 FPGA
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex™ 7 FPGA Hardware Design Example
2.1.6.1. 10GE/25GE Design Example
2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example
2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples
2.2.1. Simulation Design Examples
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components
2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components
2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.2.3. 10GE/25GE Design Example Interface Signals
2.2.4. 10GE/25GE Design Examples Registers
2.3. 100GE with Optional RS-FEC Design Example
2.3.1. Simulation Design Examples
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex™ 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex™ 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex™ 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex™ 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex™ 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.4. Ethernet Toolkit Overview
2.4.1. Features
2.5. Document Revision History for the E-Tile Hard IP for Ethernet Agilex™ 7 FPGA IP Design Example User Guide
3. E-tile CPRI PHY Intel FPGA IP Design Example
3.1. E-tile CPRI PHY Intel FPGA IP Quick Start Guide
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description
3.2.1. Features
3.2.2. Simulation Design Example
3.2.3. Hardware Design Example
3.2.4. Interface Signals
3.2.5. Design Example Register Map for Reconfiguration
3.3. Document Revision History for the E-tile CPRI PHY Intel FPGA IP Design Example User Guide
4. E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide
4.1.1. Directory Structure
4.1.2. Generating the Design
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench
4.1.3.1. Running the Simulation
4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool
4.1.3.3. Performing the Link Initialization
4.1.4. Compiling and Configuring the Design Example in Hardware
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.5.1. Running the Design Example in Hardware
4.1.5.2. Power Management Setting for Agilex™ 7 Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.2.1. Functional Description
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components
4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components
4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.2.4. 10GE/25GE Design Example Interface Signals
4.2.5. 10GE/25GE Design Examples Registers
4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.3.1. Functional Description
4.3.1.1. Clocking Scheme
4.3.1.2. Reset
4.3.2. Simulation Design Examples
4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples
4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.3.4. 25G Ethernet to CPRI Design Example Interface Signals
4.3.5. 25G Ethernet to CPRI Design Examples Registers
4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4. CPRI Dynamic Reconfiguration Design Examples
4.4.1. Functional Description
4.4.1.1. Clocking Scheme
4.4.2. Simulation Design Examples
4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.4.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples
4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4.4. CPRI Design Example Interface Signals
4.4.5. CPRI Design Example Registers
4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.2.2. Simulation Design Examples
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
4.5.3.2. Simulating the E-tile Ethernet IP for Intel Agilex™ 7 FPGA Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)]
4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)]
4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
4.5.8. Steps to Disable FEC
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives