AN 784: Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices - 2018-09-24

Version: 18.1

1. Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices
1.1. Reference Design Overview
1.1.1. Clocking Scheme
1.1.2. Memory Address Mapping
1.1.3. Floorplanning
1.2. Getting Started
1.2.1. Hardware and Software Requirements
1.2.2. Installing the Intel Arria 10 GX FPGA Development Kit
1.2.3. Installing the Linux Driver
1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components
1.3.1. BSP Top
1.3.1.1. PCI Express IP core
1.3.1.2. Intel Arria 10 DDR4 External Memory Interfaces IP Core
1.3.1.3. Design Top
1.3.1.3.1. Global Reset Logic
1.3.1.3.2. PR Region Wrapper
1.3.1.3.3. Intel Arria 10 Partial Reconfiguration Region Controller IP Core
1.3.1.3.4. Partial Reconfiguration Logic
1.4. Compiling the Reference Design
1.5. Testing the Reference Design
1.5.1. program_fpga_jtag
1.5.2. fpga-configure
1.5.3. example_host_uio
1.5.3.1. Compiling the Example Applications
1.5.3.2. Programming the Design Using Example Applications
1.6. Extending the Reference Design with Custom Persona
1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express Reference Design for Intel Arria 10 Devices
A. Reference Design Files

Back to home page