2.3. Simulation Design Example - The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI IP core when you select the Simulation or Synthesis & Simulation option. - 2025-12-29

eCPRI IP Design Example User Guide
Version
24.3
Product Type
Device Families > Agilex Families > Agilex 5
Device Families > Agilex Families > Agilex 5 > D-Series
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Agilex Families > Agilex 5 > E-Series
Device Families > Arria Families > Arria 10
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Stratix Families > Stratix 10
Device Families > Agilex Families > Agilex 7
Device Families > Arria Families
Device Families > Stratix Families
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
ft:sourceName
DITA
The eCPRI design example generates a simulation testbench and simulation files that instantiates the eCPRI IP core when you select the Simulation or Synthesis & Simulation option.
Figure 9.  eCPRI IP Simulation Block Diagram
Note: The Nios® V Subsystem block is not present in the design example generated for Arria® 10, Agilex 5, and Agilex™ 7 F-tile devices.
Figure 10.  eCPRI IP Simulation Block Diagram for Agilex 5 Devices

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.

The successful test run displays output confirming the following behavior:
  1. The client logic resets the IP core.
  2. The client logic waits for the RX datapath alignment.
  3. The client logic transmits packets on the Avalon-ST interface.
  4. Receive and checks for the content and correctness of the packets.
  5. Display "Test PASSED" message.