Nios II Processor Reference Guide - This document provides information about the Nios II processor architecture, the programming model, and the instruction set. - 2023-08-28

Product Discontinuance Notification
1. Introduction
1.1. Nios II Processor System Basics
1.2. Getting Started with the Nios II Processor
1.3. Customizing Nios II Processor Designs
1.4. Configurable Soft Processor Core Concepts
1.4.1. Configurable Soft Processor Core
1.4.2. Flexible Peripheral Set and Address Map
1.4.2.1. Standard Peripherals
1.4.2.2. Custom Components
1.4.2.3. Custom Instructions
1.4.3. Automated System Generation
1.5. Intel FPGA IP Evaluation Mode
1.6. Introduction Revision History
2. Processor Architecture
2.1. Processor Implementation
2.2. Register File
2.3. Arithmetic Logic Unit
2.3.1. Unimplemented Instructions
2.3.2. Custom Instructions
2.4. Reset and Debug Signals
2.5. Exception and Interrupt Controllers
2.5.1. Exception Controller
2.5.2. EIC Interface
2.5.3. Internal Interrupt Controller
2.6. Memory and I/O Organization
2.6.1. Instruction and Data Buses
2.6.1.1. Memory and Peripheral Access
2.6.1.2. Instruction Master Port
2.6.1.3. Data Master Port
2.6.1.4. Shared Memory for Instructions and Data
2.6.2. Cache Memory
2.6.2.1. Configurable Cache Memory Options
2.6.2.2. Effective Use of Cache Memory
2.6.2.3. Cache Bypass Methods
2.6.2.3.1. I/O Load and Store Instructions Method
2.6.2.3.2. The Bit-31 Cache Bypass Method
2.6.2.3.3. Peripheral Region
2.6.3. Tightly-Coupled Memory
2.6.3.1. Accessing Tightly-Coupled Memory
2.6.3.2. Effective Use of Tightly-Coupled Memory
2.6.4. Address Map
2.6.5. Memory Management Unit
2.6.6. Memory Protection Unit
2.7. JTAG Debug Module
2.7.1. JTAG Target Connection
2.7.2. Download and Execute Software
2.7.3. Software Breakpoints
2.7.4. Hardware Breakpoints
2.7.5. Hardware Triggers
2.7.5.1. Armed Triggers
2.7.5.2. Triggering on Ranges of Values
2.7.6. Trace Capture
2.7.6.1. Execution vs. Data Trace
2.7.6.2. Trace Frames
2.8. Processor Architecture Revision History
3. Programming Model
3.1. Operating Modes
3.1.1. Supervisor Mode
3.1.2. User Mode
3.2. Memory Management Unit
3.2.1. Recommended Usage
3.2.2. Memory Management
3.2.2.1. Virtual Addressing
3.2.2.2. Memory Protection
3.2.3. Address Space and Memory Partitions
3.2.3.1. Virtual Memory Address Space
3.2.3.2. Physical Memory Address Space
3.2.3.3. Data Cacheability
3.2.4. TLB Organization
3.2.5. TLB Lookups
3.3. Memory Protection Unit
3.3.1. Memory Regions
3.3.1.1. Base Address
3.3.1.2. Region Type
3.3.1.3. Region Index
3.3.1.4. Region Size or Upper Address Limit
3.3.1.5. Access Permissions
3.3.1.6. Default Cacheability
3.3.2. Overlapping Regions
3.3.3. Enabling the MPU
3.4. Registers
3.4.1. General-Purpose Registers
3.4.2. Control Registers
3.4.2.1. The status Register
3.4.2.2. The estatus Register
3.4.2.3. The bstatus Register
3.4.2.4. The ienable Register
3.4.2.5. The ipending Register
3.4.2.6. The cpuid Register
3.4.2.7. The exception Register
3.4.2.8. The pteaddr Register
3.4.2.9. The tlbacc Register
3.4.2.10. The tlbmisc Register
3.4.2.10.1. The RD Flag
3.4.2.10.2. The WE Flag
3.4.2.10.3. The WAY Field
3.4.2.10.4. The PID Field
3.4.2.10.5. The DBL Flag
3.4.2.10.6. The BAD Flag
3.4.2.10.7. The PERM Flag
3.4.2.10.8. The D Flag
3.4.2.11. The badaddr Register
3.4.2.12. The config Register
3.4.2.13. The mpubase Register
3.4.2.14. The mpuacc Register
3.4.2.14.1. The MASK Field
3.4.2.14.2. The LIMIT Field
3.4.2.14.3. The MT Flag
3.4.2.14.4. The PERM Field
3.4.2.14.5. The RD Flag
3.4.2.14.6. The WR Flag
3.4.2.14.7. The eccinj Register
3.4.3. Shadow Register Sets
3.4.3.1. The sstatus Register
3.4.3.1.1. Changing Register Sets
3.4.3.1.2. Stacks and Shadow Register Sets
3.4.3.2. Initialization with Shadow Register Sets
3.5. Working with the MPU
3.5.1. MPU Region Read and Write Operations
3.5.2. MPU Initialization
3.5.3. Debugger Access
3.6. Working with ECC
3.6.1. Enabling ECC
3.6.1.1. Disabling ECC
3.6.2. Handling ECC Errors
3.6.3. Injecting ECC Errors
3.6.3.1. Instruction Cache Tag RAM
3.6.3.2. Instruction Cache Data RAM
3.6.3.3. ITCMs
3.6.3.4. Register File RAM Blocks
3.6.3.5. Data Cache Tag RAM
3.6.3.6. Data Cache Data RAM (Clean Line)
3.6.3.7. Data Cache Data RAM (Dirty Line)
3.6.3.8. Data Cache Victim Line Buffer RAM
3.6.3.9. DTCMs
3.6.3.10. MMU TLB RAM
3.7. Exception Processing
3.7.1. Terminology
3.7.2. Exception Overview
3.7.3. Exception Latency
3.7.3.1. Interrupt Latency
3.7.4. Reset Exceptions
3.7.5. Break Exceptions
3.7.5.1. Processing a Break
3.7.5.2. Understanding Register Usage
3.7.5.3. Returning From a Break
3.7.6. Interrupt Exceptions
3.7.6.1. External Interrupt Controller Interface
3.7.6.1.1. Requested Handler Address
3.7.6.1.2. Requested Interrupt Level
3.7.6.1.3. Requested Register Set
3.7.6.1.4. Requested NMI Mode
3.7.6.1.5. Shadow Register Sets
3.7.6.2. Internal Interrupt Controller
3.7.7. Instruction-Related Exceptions
3.7.7.1. Trap Instruction
3.7.7.2. Break Instruction
3.7.7.3. Unimplemented Instruction
3.7.7.4. Illegal Instruction
3.7.7.5. Supervisor-Only Instruction
3.7.7.6. Supervisor-Only Instruction Address
3.7.7.7. Supervisor-Only Data Address
3.7.7.8. Misaligned Data Address
3.7.7.9. Misaligned Destination Address
3.7.7.10. Division Error
3.7.7.11. Fast TLB Miss
3.7.7.12. Double TLB Miss
3.7.7.13. TLB Permission Violation
3.7.7.14. MPU Region Violation
3.7.8. Other Exceptions
3.7.9. Exception Processing Flow
3.7.9.1. Processing General Exceptions
3.7.9.2. Exception Flow with the EIC Interface
3.7.9.3. Exception Flow with the Internal Interrupt Controller
3.7.9.4. Exceptions and Processor Status
3.7.10. Determining the Cause of Interrupt and Instruction-Related Exceptions
3.7.10.1. Nios II/f Exception Processing
3.7.10.2. Nios II/e Exception Processing
3.7.11. Handling Nested Exceptions
3.7.11.1. Nested Exceptions with the Internal Interrupt Controller
3.7.11.2. Nested Exceptions with an External Interrupt Controller
3.7.12. Handling Nonmaskable Interrupts
3.7.13. Masking and Disabling Exceptions
3.7.13.1. Disabling Maskable Interrupts
3.7.13.2. Masking Interrupts with an External Interrupt Controller
3.7.13.3. Masking Interrupts with the Internal Interrupt Controller
3.7.13.4. Returning From Interrupt and Instruction-Related Exceptions
3.7.13.4.1. Return Address Considerations
3.8. Memory and Peripheral Access
3.8.1. Cache Memory
3.8.1.1. Virtual Address Aliasing
3.9. Instruction Set Categories
3.9.1. Data Transfer Instructions
3.9.2. Arithmetic and Logical Instructions
3.9.3. Move Instructions
3.9.4. Comparison Instructions
3.9.5. Shift and Rotate Instructions
3.9.6. Program Control Instructions
3.9.7. Other Control Instructions
3.9.8. Custom Instructions
3.9.9. No-Operation Instruction
3.9.10. Potential Unimplemented Instructions
3.10. Programming Model Revision History
4. Instantiating the Nios II Processor
4.1. Main Nios II Tab
4.2. Vectors Tab
4.2.1. Reset Vector
4.2.2. Exception Vector
4.2.3. Fast TLB Miss Exception Vector
4.3. Caches and Memory Interfaces Tab
4.3.1. Instruction Cache
4.3.2. Flash Accelerator
4.3.3. Data Cache
4.3.4. Tightly-coupled Memories
4.3.5. Peripheral Region
4.4. Arithmetic Instructions Tab
4.4.1. Arithmetic Instructions
4.4.2. Arithmetic Implementation
4.5. MMU and MPU Settings Tab
4.5.1. MMU
4.5.2. MPU
4.6. JTAG Debug Tab
4.7. Advanced Features Tab
4.7.1. ECC
4.7.2. Interrupt Controller Interfaces
4.7.3. Shadow Register Sets
4.7.4. Reset Signals
4.7.5. CPU ID Control Register Value
4.7.6. Generate Trace File
4.7.7. Exception Checking
4.7.8. Branch Prediction
4.7.9. RAM Memory Protection
4.8. The Quartus Prime IP File
4.9. Instantiating the Nios II Processor Revision History
5. Nios II Core Implementation Details
5.1. Device Family Support
5.2. Nios II/f Core
5.2.1. Overview
5.2.2. Arithmetic Logic Unit
5.2.2.1. Multiply and Divide Performance
5.2.2.2. Shift and Rotate Performance
5.2.3. Memory Access
5.2.3.1. Instruction and Data Master Ports
5.2.3.2. Instruction and Data Caches
5.2.3.2.1. Instruction Cache
5.2.3.2.2. Data Cache
5.2.3.2.3. Bursting
5.2.4. Tightly-Coupled Memory
5.2.5. Memory Management Unit
5.2.5.1. Micro Translation Lookaside Buffers
5.2.6. Memory Protection Unit
5.2.7. Execution Pipeline
5.2.7.1. Pipeline Stalls
5.2.7.2. Branch Prediction
5.2.8. Instruction Performance
5.2.9. Exception Handling
5.2.9.1. External Interrupt Controller Interface
5.2.10. ECC
5.2.11. JTAG Debug Module
5.3. Nios II/s Core
5.3.1. Overview
5.3.2. Arithmetic Logic Unit
5.3.2.1. Multiply and Divide Performance
5.3.2.2. Shift and Rotate Performance
5.3.3. Memory Access
5.2.3.1. Instruction and Data Master Ports
5.3.3.2. Instruction Cache
5.3.4. Tightly-Coupled Memory
5.3.5. Execution Pipeline
5.3.5.1. Pipeline Stalls
5.3.5.2. Branch Prediction
5.3.6. Instruction Performance
5.3.7. Exception Handling
5.3.8. JTAG Debug Module
5.4. Nios II/e Core
5.4.1. Overview
5.4.2. Arithmetic Logic Unit
5.4.3. Memory Access
5.4.4. Instruction Execution Stages
5.4.5. Instruction Performance
5.4.6. Exception Handling
5.4.7. JTAG Debug Module
5.5. Nios II Core Implementation Details Revision History
6. Nios II Processor Versions
6.1. Nios II Versions Revision History
6.2. Architecture Revisions
6.3. Core Revisions
6.3.1. Nios II/f Core
6.3.2. Nios II/s Core
6.3.3. Nios II/e Core
6.4. JTAG Debug Module Revisions
6.5. Nios II Processor Versions Revision History
7. Application Binary Interface
7.1. Data Types
7.2. Memory Alignment
7.3. Register Usage
7.4. Stacks
7.4.1. Frame Pointer Elimination
7.4.2. Call Saved Registers
7.4.3. Further Examples of Stacks
7.4.3.1. Stack Frame for a Function With alloca()
7.4.3.2. Stack Frame for a Function with Variable Arguments
7.4.3.3. Stack Frame for a Function with Structures Passed By Value
7.4.4. Function Prologues
7.4.4.1. Prologue Variations
7.5. Arguments and Return Values
7.5.1. Arguments
7.5.2. Return Values
7.6. DWARF-2 Definition
7.7. Object Files
7.8. Relocation
7.9. ABI for Linux Systems
7.9.1. Linux Toolchain Relocation Information
7.9.1.1. Copy Relocation
7.9.1.2. Jump Slot Relocation
7.9.1.3. Thread-Local Storage
7.9.2. Linux Function Calls
7.9.3. Linux Operating System Call Interface
7.9.4. Linux Process Initialization
7.9.5. Linux Position-Independent Code
7.9.6. Linux Program Loading and Dynamic Linking
7.9.6.1. Global Offset Table
7.9.6.2. Function Addresses
7.9.6.3. Procedure Linkage Table
7.9.6.4. Linux Program Interpreter
7.9.6.5. Linux Initialization and Termination Functions
7.9.7. Linux Conventions
7.9.7.1. System Calls
7.9.7.2. Userspace Breakpoints
7.9.7.3. Atomic Operations
7.9.7.4. Processor Requirements
7.10. Development Environment
7.11. Application Binary Interface Revision History
8. Instruction Set Reference
8.1. Word Formats
8.1.1. I-Type
8.1.2. R-Type
8.1.3. J-Type
8.2. Instruction Opcodes
8.3. Assembler Pseudo-Instructions
8.4. Assembler Macros
8.5. Instruction Set Reference
8.5.1. add
8.5.2. addi
8.5.3. and
8.5.4. andhi
8.5.5. andi
8.5.6. beq
8.5.7. bge
8.5.8. bgeu
8.5.9. bgt
8.5.10. bgtu
8.5.11. ble
8.5.12. bleu
8.5.13. blt
8.5.14. bltu
8.5.15. bne
8.5.16. br
8.5.17. break
8.5.18. bret
8.5.19. call
8.5.20. callr
8.5.21. cmpeq
8.5.22. cmpeqi
8.5.23. cmpge
8.5.24. cmpgei
8.5.25. cmpgeu
8.5.26. cmpgeui
8.5.27. cmpgt
8.5.28. cmpgti
8.5.29. cmpgtu
8.5.30. cmpgtui
8.5.31. cmple
8.5.32. cmplei
8.5.33. cmpleu
8.5.34. cmpleui
8.5.35. cmplt
8.5.36. cmplti
8.5.37. cmpltu
8.5.38. cmpltui
8.5.39. cmpne
8.5.40. cmpnei
8.5.41. custom
8.5.42. div
8.5.43. divu
8.5.44. eret
8.5.45. flushd
8.5.46. flushda
8.5.47. flushi
8.5.48. flushp
8.5.49. initd
8.5.50. initda
8.5.51. initi
8.5.52. jmp
8.5.53. jmpi
8.5.54. ldb / ldbio
8.5.55. ldbu / ldbuio
8.5.56. ldh / ldhio
8.5.57. ldhu / ldhuio
8.5.58. ldw / ldwio
8.5.59. mov
8.5.60. movhi
8.5.61. movi
8.5.62. movia
8.5.63. movui
8.5.64. mul
8.5.65. muli
8.5.66. mulxss
8.5.67. mulxsu
8.5.68. mulxuu
8.5.69. nextpc
8.5.70. nop
8.5.71. nor
8.5.72. or
8.5.73. orhi
8.5.74. ori
8.5.75. rdctl
8.5.76. rdprs
8.5.77. ret
8.5.78. rol
8.5.79. roli
8.5.80. ror
8.5.81. sll
8.5.82. slli
8.5.83. sra
8.5.84. srai
8.5.85. srl
8.5.86. srli
8.5.87. stb / stbio l
8.5.88. sth / sthio
8.5.89. stw / stwio
8.5.90. sub
8.5.91. subi
8.5.92. sync
8.5.93. trap
8.5.94. wrctl
8.5.95. wrprs
8.5.96. xor
8.5.97. xorhi
8.5.98. xori
8.6. Instruction Set Reference Revision History

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