The following timing diagram illustrates a successful PR operation with Partial Reconfiguration Controller
Arria® 10
/Cyclone 10 IP. The status[2:0] output signal indicates whether the operations passes or fails. The PR operation initiates upon assertion of the pr_start signal. Monitor the status[] signal to detect the end of the PR operation.
Figure 60.
Partial Reconfiguration Controller
Arria® 10/Cyclone 10 IP Timing Specifications
The following notes correspond to locations (1) through (7) in the timing diagram:
- Assert pr_start signal high for a minimum of one clock cycle to initiate PR. Deassert pr_start before sending the last data.
- status[] signal updates after pr_start is acknowledged. This signal changes during a PR operation if CRC_ERROR, PR_ERROR, or bitstream incompatibility error occurs.
- status[] signal changes after a PR operation if CRC_ERROR asserts and no error occurs during the previous PR operation.
- There is no requirement to assert the data_valid signal at the same time as the pr_start signal. Provide the data[], and assert data_valid, when appropriate.
- Either drive the data_valid signal low after sending the last data, or continue to assert data_valid high with dummy data on data[] until the IP reads the end of PR from status[].
- data[] transfers only when data_valid and data_ready assert on the same cycle. Do not drive new data on the data bus, when both data_valid and data_ready are not high.
- The data_ready signal drives low after the PR IP Controller core receives the last data, or when the PR IP Controller cannot accept data.