The interface between partial and static partitions remains the same for each PR implementation revision. Perform timing analysis on each PR implementation revision to ensure that there are no timing violations. To ensure timing closure of a design with multiple PR regions, you can create aggregate revisions for all possible PR region combinations for timing analysis.
Note:
Logic Lock regions impose placement constraints that affect the performance
and resource utilization of your PR design. Ensure that the design has additional timing
allowance and available device resources. Selecting the largest and most timing-critical
persona as your base persona optimizes the timing closure. In addition, if you compile the
base design with time borrowing enabled, compile the implementation designs with time
borrowing enabled. Otherwise, time borrowing amounts in the base design are reset to zero, and
the design may not pass timing. If this condition occurs, you can use the update_timing_netlist –recompute_borrow command to restore time
borrowing amounts throughout the design for timing analysis.