3.2.1. Memory Map - The Partial Reconfiguration Controller Altera IP has the following memory map. - 2026-02-19

Quartus Prime Pro Edition User Guide Partial Reconfiguration

Version: 25.1

The Partial Reconfiguration Controller Altera^® IP has the following memory map.

Table 12. Avalon^® Memory-Mapped Agent Memory Map
Name	Address Offset	Width	Access	Description
`PR_DATA`	0x00	32	Write	Every data `write` to this address indicates this bitstream is sending to the IP core. Width is set by the Input data width parameter.
`PR_CSR`	0x01	32	Read or Write	Control and status registers with the following offset bits: 31 - 7: Reserved. 6: Protocol violation. This bit is asserted when the Avalon memory-mapped or Avalon streaming protocol is violated. 5: Read/Write for `irq` signal mask bit. Write `1` to this bit enable `irq` signal and `0` to disable the `irq` signal. 4: Read/Clear for `irq` signal. The `irq` signal asserts if an error occurs. The host must read the status signal and clear the interrupt by writing `1` to this bit. 3 - 1: Read-only for `status` signal. 0: Read/Write for `pr_start` signal. To streamline the flow, the IP core automatically de-asserts to value `0`, one clock cycle after the signal asserts.
`PR_SW_VER`	0x02	32	Read	Read-only SW version register. Register is currently 0xBA500000.
`PR_FW_HANDSHAKE`	0x03	32	Read	Current location of mailbox handshake between the PR IP and the SDM in the PR operation with the following offset bits: 31 - 8: Reserved. 7 - 0: Current location of the mailbox handshake between the PR IP and the SDM.
`PR_FW_RESPONSE`	0x04	32	Read	SDM mailbox response. You must use this in conjunction with `PR_FW_HANDSHAKE`. If `PR_FW_HANDSHAKE` is `0x2` or `0x6`, the following offset bits apply: 31 - 11: Reserved. 10 - 0: Response header of the response payload. If `PR_FW_HANDSHAKE` is 0x4, the following offset bit applies: 31 - 0: First response word of response payload.

Note: For IP core instantiation guidelines, refer to the appropriate device configuration user guide.