2.3.10. Configuring an External Host for Arria 10 or Cyclone 10 GX Designs - When using external host configuration, the external host initiates partial reconfiguration, and monitors the PR status using the external PR dedicated pins during user mode. In this mode, the external host must respond appropriately to the handshake signals for successful partial reconfiguration. The external host writes the partial bitstream data from external memory into the Arria 10 or Cyclone 10 GX device. Co-ordinate system-level partial reconfiguration by ensuring that you prepare the correct PR region for partial reconfiguration. After reconfiguration, return the PR region into operating state.

When using external host configuration, the external host initiates partial reconfiguration, and monitors the PR status using the external PR dedicated pins during user mode. In this mode, the external host must respond appropriately to the handshake signals for successful partial reconfiguration. The external host writes the partial bitstream data from external memory into the Arria^® 10 or Cyclone^® 10 GX device. Co-ordinate system-level partial reconfiguration by ensuring that you prepare the correct PR region for partial reconfiguration. After reconfiguration, return the PR region into operating state.

To use an external host for your design:

Click Assignments > Device > Device & Pin Options.
Select the Enable PR Pins option in the Device & Pin Options dialog box. This option automatically creates the special partial reconfiguration pins, and defines the pins in the device pin-out. This option also automatically connects the pins to PR control block internal path.
Note: If you do not select this option, you must use an internal or HPS host. You do not need to define pins in your design top-level entity.
Connect these top-level pins to the specific ports in the PR control block.

The following table lists the PR pins that automatically constrain when you turn on Enable PR Pins, and the specific PR control block port connection to the pin:

Table 32. Partial Reconfiguration Dedicated Pins
Pin Name	Type	PR Control Block Port Name	Description
`PR_REQUEST`	Input	`prrequest`	Logic high on this pin indicates that the PR host is requesting partial reconfiguration.
`PR_READY`	Output	`ready`	Logic high on this pin indicates that the PR control block is ready to begin partial reconfiguration.
`PR_DONE`	Output	`done`	Logic high on this pin indicates that the partial reconfiguration is complete.
`PR_ERROR`	Output	`error`	Logic high on this pin indicates an error in the device during partial reconfiguration.
`DATA[31:0]`	Input	`data`	These pins provide connectivity for `PR_DATA` to transfer the PR bitstream to the PR controller.
`DCLK`	Input	`clk`	Receives synchronous `PR_DATA`.

Note:

PR_DATA can be 8, 16, or 32-bits in width.
Ensure that you connect the corectl port of the PR control block to 0.

Verilog RTL for External Host PR

module top(
     // PR control block signals
     input  logic        pr_clk,
     input  logic        pr_request,
     input  logic [31:0] pr_data,
     output logic        pr_error,
     output logic        pr_ready,
     output logic        pr_done,

     // User signals
     input  logic i1_main,
     input  logic i2_main,
     output logic o1
);

// Instantiate the PR control block
twentynm_prblock m_prblock
(
    .clk(pr_clk),
    .corectl(1'b0),
    .prrequest(pr_request),
    .data(pr_data),
    .error(pr_error),
    .ready(pr_ready),
    .done(pr_done)
);


// PR Interface partition
pr_v1 pr_inst(
   .i1(i1_main),
   .i2(i2_main),
   .o1(o1)
);

endmodule

VHDL RTL for External Host PR

library ieee;
use ieee.std_logic_1164.all;

entity top is
port(
      -- PR control block signals
      pr_clk: in std_logic;
      pr_request: in std_logic;
      pr_data: in std_logic_vector(31 downto 0);
                
      pr_error: out std_logic;
      pr_ready: out std_logic;
      pr_done: out std_logic;
                
      -- User signals
      i1_main: in std_logic;
      i2_main: in std_logic;
      o1: out std_logic
);
end top;

architecture behav of top is

component twentynm_prblock is
port(      
      clk: in std_logic;
      corectl: in std_logic;
      prrequest: in std_logic;
      data: in std_logic_vector(31 downto 0);
      error: out std_logic;
      ready: out std_logic;
      done: out std_logic
);
end component;

component pr_v1 is
port(     
      i1: in std_logic;
      i2: in std_logic;
      o1: out std_logic
);
end component;

signal pr_gnd : std_logic;

begin

pr_gnd <= '0';

-- Instantiate the PR control block
m_prblock: twentynm_prblock port map
(
    pr_clk,
    pr_gnd,
    pr_request,
    pr_data,
    pr_error,
    pr_ready,
    pr_done
);


-- PR Interface partition
pr_inst : pr_v1 port map
(
   i1_main,
   i2_main,
   o1
);

end behav;