AN 846: Stratix 10 Forward Error Correction - Explains forward error correction (FEC) theory and the Stratix 10 device family's FEC capabilities. - 2018-07-02

1. Introduction
2. Necessity of Error Correction
2.1. Solutions to Transmission Errors
2.1.1. Parity and Cyclic Redundancy Check
2.1.2. Error Correction Code (ECC) Block Coding
2.2. Error Correction Codes
2.3. What is FEC?
2.3.1. FEC Definitions
3. FEC Selection
3.1. Key Considerations when Choosing a FEC
4. FEC in Stratix 10 H-Tile Devices
4.1. Fire Code (802.3ap, 10GBASE-KR)
4.1.1. FEC Block Format
4.1.2. FEC Block Composition
4.1.3. FEC Sublayer for BASE-R PHYs
4.1.4. L-Tile/H-Tile Implementation
4.1.4.1. Transcode Encoder
4.1.4.2. KR FEC Encoder
4.1.4.3. KR FEC Scrambler
4.1.4.4. KR FEC TX Gearbox
4.1.4.5. KR FEC RX Gearbox
4.1.4.6. Transcode Decoder
5. FEC in Stratix 10 E-Tile Devices
5.1. Types of RS-FEC
5.1.1. RS (528, 514, t = 7, m = 10)
5.1.2. RS (544, 514, t = 15, m = 10)
5.1.3. Supported RS-FEC Modes in E-Tile Devices
5.2. 100GBASE-KR4
5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
5.3. 100GBASE-KP4
5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
5.4. FEC Decoders
5.5. Specifications
5.6. Functions Within the RS-FEC Sublayer
5.6.1. Lane Block Synchronization
5.6.2. Alignment Lock and Deskew
5.6.3. Lane Re-order
5.6.4. Alignment Marker Removal
5.6.5. 64B/66B to 256B/257B Transcoder
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
7.1. Datacenter Applications Scenario
8. Hardware Results
8.1. Test Design
8.2. Test Setup
8.3. Insertion Loss Plots
8.4. FEC Statistics Tool
8.5. Hardware Data
8.6. Comparison to the Specification
8.7. References
9. Document Revision History for AN 846: Stratix 10 Forward Error Correction

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