1.3. Simulating the Design Example Testbench - You can compile and simulate the design by running a simulation script from the command prompt. - 2025-12-18

F-Tile Ethernet Hard IP Design Example User Guide
Version
24.3
You can compile and simulate the design by running a simulation script from the command prompt.
Figure 8. Procedure
  1. At the command prompt, change the working directory to <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench displays "Simulation Passed".
    Table 5.  Steps to Simulate the Testbench
    Simulator Instructions
    Synopsys® VCS® In the command line, type:
    sh run_vcs.sh
    Synopsys® VCS® MX In the command line, type:
    sh run_vcsmx.sh

    Use this script when the design contains Verilog HDL and System Verilog with VHDL.
    ModelSim® SE or QuestaSIM® or Questa®-Altera® FPGA Edition 1 In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type:
    vsim -c -do run_vsim.do
    Xcelium™ In the command line, type:
    sh run_xcelium.sh
    Aldec Riviera-PRO™ 2 In the command line, type 
    vsim -c -do run_rivierasim.do
A successful simulation ends with the following message:
Simulation Passed.
or
Testbench complete.
After successful completion, you can analyze the results.
1 Questafe simulator is not supported for F-Tile AN/LT IP designs.
2 Only Riviera 2022.10 is supported