1.1.1. Generating Single IP Instance Design - 2025-12-18

F-Tile Ethernet Hard IP Design Example User Guide
Version
24.3
Figure 2. Procedure

  1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Agilex™ 7 (F-Series/I-Series) and select device with F-Tile for your design.
  3. Select Tools > IP Catalog to open the IP Catalog and select F-Tile Ethernet Hard IP .
  4. Specify a top-level name <your_ip> and the folder for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  5. Click Create. The IP parameter editor appears.
    Figure 3. Example Design Tab
  6. On the IP tab, specify the parameters for your IP core variation. For exact IP parameter setting, refer to the Selected IP Parameter Settings table in the desired Design Example chapter.
  7. Specify the parameters in the Example Design tab.

Table 1.  Single Instance of IP Core Design Example Parameters
Parameters Value Description
Select Design

Single Instance of IP Core

 Selects the single instance of IP core for example design.
Example Design Files

Simulation

Synthesis

Enable Signal Tap for Debug
  • Simulation option generates the testbench and compilation-only project.
  • Synthesis option generates the hardware design example.
  • Enable Signal Tap for Debug option generates a standard signal tap file. This option is available only for a single IP instance and when AN/LT is disabled.
Simulation Options

Enable fast Simulation

Enable Optimized Auto-Negotiation and Link Training full simulation

 Enables fast simulation for Ethernet IP in generated example design. When AN/LT is enabled, It also enables the fast simulation in AN/LT IP.

Enable Optimized Auto-Negotiatin and Link Training full simulation option enables the optimized simulation for full auto-negotiation and link training flow in generated example design. This option cannot be enabled along with Enable Fast Simulation.
Generated File Format Verilog

VHDL

 Select the HDL files format. If you select VHDL, you must simulate the testbench with a mixed-language simulator.
Target Development Kit None

Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile)

Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (ES 1 4x F-Tile)

 Select Device Initialization Clock for the Target development kit option specifies the target development kit used to generate the project.
  1. Click the Generate Example Design button.
The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing.
Related Information