AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families - 2018-07-31

Implementing Bus LVDS Interface in Supported Intel FPGA Device Families
BLVDS Overview
Design Considerations
Effective Impedance
Propagation Delay
BLVDS Technology in Intel Devices
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Power Consumption
BLVDS Design Example
Design Example Guidelines for Intel Stratix 10 Devices
Design Example Guidelines for Intel Arria 10 Devices
Design Example Guidelines for Intel MAX 10 Devices
Design Example Guidelines for All Supported Devices Except Intel Arria 10, Intel Cyclone 10 GX, and Intel MAX 10
Performance Analysis
System Setup
Bus Termination
Stub Length
Stub Termination
Driver Slew Rate
Overall System Performance
Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families

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