1.2. Directory Structure - 2025-12-15

Interlaken (2nd Generation) Agilex™ 7 FPGA IP Design Example User Guide
Version
23.4
The Interlaken (2nd Generation) IP core design example file directories contain the following generated files for the design example.
Figure 3. Directory Structure of the Generated Interlaken (2nd Generation) Example Design

The hardware configuration, simulation, and test files are located in

<design_example_installation_dir>/uflex_ilk_0_example_design.

Table 1.   Interlaken (2nd Generation) IP Core Hardware Design Example File DescriptionsThese files are in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/quartus directory.
File Names Description
example_design.qpf Quartus® Prime project file.
example_design.qsf Quartus® Prime project settings file
example_design.sdc

jtag_timing_template.sdc

Synopsys Design Constraint file. You can copy and modify for your own design.
sysconsole_testbench.tcl Main file for accessing System Console
Table 2.   Interlaken (2nd Generation) IP Core Testbench File DescriptionThis file is in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/rtl directory.
File Name Description
top_tb.sv Top-level testbench file.
Table 3.   Interlaken (2nd Generation) IP Core Testbench ScriptsThese files are in the <design_example_installation_dir>/uflex_ilk_0_example_design/example_design/testbench directory.
File Name Description
vcstest.sh The VCS® script to run the testbench.
vlog_pro.do The Questa*-Intel® FPGA Edition or QuestaSIM® script to run the testbench.
xcelium.sh The Xcelium™ script to run the testbench.