MAX 10 FPGA Device Datasheet - The Intel MAX 10 device datasheet covers the electrical characteristics, switching characteristics, configuration specifications, and timing specifications for Intel MAX 10 devices. - 2022-10-31
Product Type
Device Families > MAX Families > MAX 10
Device Families > MAX Families
Resource Type
Documentation > Product Specifications > Data Sheets
Source Name
DITA
Intel MAX 10 FPGA Device Datasheet
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings
Single Supply Devices Absolute Maximum Ratings
Dual Supply Devices Absolute Maximum Ratings
Absolute Maximum Ratings
Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame
Recommended Operating Conditions
Single Supply Devices Power Supplies Recommended Operating Conditions
Dual Supply Devices Power Supplies Recommended Operating Conditions
Recommended Operating Conditions
Programming/Erasure Specifications
DC Characteristics
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Parameters
Series OCT without Calibration Specifications
Series OCT with Calibration at Device Power-Up Specifications
OCT Variation after Calibration at Device Power-Up
Pin Capacitance
Internal Weak Pull-Up Resistor
Hot-Socketing Specifications
Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
Switching Characteristics
Core Performance Specifications
Clock Tree Specifications
PLL Specifications
Embedded Multiplier Specifications
Memory Block Performance Specifications
Internal Oscillator Specifications
UFM Performance Specifications
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications
Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications
High-Speed I/O Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Emulated RSDS_E_1R Transmitter Timing Specifications
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
True LVDS Transmitter Timing
Single Supply Devices True LVDS Transmitter Timing Specifications
Dual Supply Devices True LVDS Transmitter Timing Specifications
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Single Supply Devices LVDS Receiver Timing Specifications
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Memory Standards Supported by the Soft Memory Controller
Memory Output Clock Jitter Specifications
Configuration Specifications
JTAG Timing Parameters
Remote System Upgrade Circuitry Timing Specifications
User Watchdog Internal Circuitry Timing Specifications
Uncompressed Raw Binary File (.rbf) Sizes
Internal Configuration Time
Internal Configuration Timing Parameter
I/O Timing
Programmable IOE Delay
Programmable IOE Delay On Row Pins
Programmable IOE Delay for Column Pins
Glossary
Document Revision History for the Intel MAX 10 FPGA Device Datasheet