6.1.1. Generating the Synthesis HDL Files - Follow these steps to generate the synthesis HDL files for P-Tile, R-Tile, or F-Tile PCI Express with CvP enabled: - 2025-12-16

Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
Version
23.1
Follow these steps to generate the synthesis HDL files for P-Tile, R-Tile, or F-Tile PCI Express® with CvP enabled:
  1. Open the Quartus® Prime Pro Edition software.
  2. On the Tools menu, click Platform Designer . The Open System window appears.
  3. For System, click + and specify a File Name to create a new platform designer system. Click Create.
  4. On the System Contents tab, delete the clock_in and reset_in components that appear by default.
  5. In the IP Catalog locate and double-click the PCI Express® tile of your choice. The new window appears.
    Note: For P-Tile, select P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express® .
    Note: For R-Tile, select R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express® .
    Note: For F-Tile, select F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express® .
  6. On the IP Settings tab, specify the parameters and options for your design variation.
  7. On the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For R-Tile Avalon® streaming interface for PCI Express, on the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For F-Tile Avalon® streaming interface for PCI Express, on the PCIe0 Settings -> PCIe0 PCI Express/ PCI Capabilities -> PCIe0 VSEC tab, select the Enable CVP (Intel VSEC) option.
    Note: For devices that support two PCIe Hard IP block on the left, CvP application can use either one of the two PCIe Hard IP blocks on left side. This option is to enable the CvP application to either lower or upper PCIe Hard block. Subsequently, you must do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
  8. If PCIe® 3.0 2x8 or PCIe® 4.0 2x8 mode is used, on the PCIe® 0 Settings tab, leave the Device ID as 0x00000000, on the PCIe® 1 settings, set the Device ID to non-zero value. In this mode, only PCIe® 0 or Port 0 can be used for CvP application, and the CvP driver checks for Device ID and registers Port 0 as CvP device if the Device ID is set to zero.
  9. On the Example Designs tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
  10. For Generated file format, only Verilog is available.
  11. Click the Generate Example Design button. The Select Example Design Directory dialog box appears. Click OK. The software generates Quartus® Prime project files for PCI Express® reference design.

    Click Close when generation completes. An example design is created in your project directory.

  12. Click Finish. Close your current project and open the generated PCI Express example design (pcie_ed.qpf).
  13. Complete your CvP design by adding any desired top-level design and any other required modules. You must ensure you do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
    Note: Reference design for CvP initialization and update is not available in the current version of the Quartus® Prime software.
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