8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide - 2025-12-16

Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide
Version
23.1
Document Version Quartus® Prime Version Changes
2025.07.31 23.1 Updated the numbered explanation below the CvP Block Diagram figure in the CvP System section.
2025.01.23 23.1 Added reference to the Agilex™ 7 SoC FPGA Boot User Guide in the following sections:
  • CvP Limitations
  • CvP Update Mode
2024.10.02 23.1
  • Updated row C in the Power-Up Sequence Timing in CvP Initialization Mode table.
  • Updated the FPGA Power Supplies Ramp-Up Time and POR figure in the FPGA Power Supplies Ramp Time Requirement section.
2024.07.03 23.1 Updated the label in PCIe® Timing Sequence in CvP Initialization Mode figure to FPGA Bottom Left or Top Left Transceiver Status.
2024.04.01 23.1 Added a footnote about delay before configuration in the Setting Up the Correct MSEL Switch State section.
2023.12.04 23.1
  • Updated CvP Modes section as per the following:
    • Updated PCIe® Version details in CvP Support for Agilex™ 7 Device Family table.
    • Updated Bifurcation PCIe® Mode Version details in the table in the note.
    • Updated notes.
  • Updated CvP Initialization Mode section.
  • Updated Pin Description section.
  • Updated PCIe® Timing Sequence in CvP Initialization Mode figure in For CvP Initialization Mode section.
  • Updated Timing Range in Power-Up Sequence Timing in CvP Initialization Mode table in For CvP Initialization Mode section.
  • Added note after Power-Up Sequence Timing in CvP Initialization Mode table in For CvP Initialization Mode section.
  • Updated title for Generating the Synthesis HDL files for Intel FPGA P-Tile Avalon® streaming interface for PCI Express® section to Generating the Synthesis HDL files for Supported PCIe® Tile.
  • Updated steps 5 and 11 in Generating the Synthesis HDL files for Supported PCIe® Tile section.
  • Added additional related information in Generating the Synthesis HDL files for Supported PCIe® Tile section.
  • Updated footnote for the Configuration Scheme in MSEL Pin Settings for Active Serial x4 (Fast mode) Scheme of Agilex™ 7 Devices table in Setting Up the Correct MSEL Switch State section.
2023.08.17 23.1 Updated the recommended QSPI flash size for periphery images in the Configuration Images section.
2023.07.07 23.1
  • Added description on periphery image in Configuration Images section.
  • Added Intel Premier Support ID in Designing CvP for a Closed System section.
2023.04.10 23.1
  • Added PCIe® Version details for R-Tile and F-tile in the CvP Support for Intel Agilex Device Family table.
  • Updated the third note in the CvP Modes section.
  • Updated first bullet point and added a new bullet point in the CvP Limitations section regarding CvP in designs that include the Hard Processor System (HPS).
  • Updated the CvP Update Modesection to include information regarding how performing an FPGA core image update affects the HPS.
  • Updated product family name to " Intel Agilex® 7".
  • Replaced "Avalon-ST" with "Avalon streaming interface".
  • Replaced "Avalon-MM" with "Avalon memory mapped".
2022.12.19 22.4
  • Updated the naming scheme from Gen<X> to PCIe® <X>.0 throughout the document.
  • Updated PCIe® Version details for P-Tile Supported Tile in the CvP Support for Intel Agilex Device Family table.
  • Updated CvP Error Recovery section.
  • Updated Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express section.
2022.09.26 22.2 Added second note under image in the Implementation of CvP Update Mode section.
2022.08.05 22.2
  • Made changes to the following sections to remove downstream driver support.
    • Updated:
      • CvP Modes
      • CvP Driver Support
      • Installing the Upstream Open Source CvP Driver on Linux Systems
      • Programming CvP Options
      • Programming the Core RBF file from the Updated Revision via PCIe Link
    • Removed:
      • Installing Open Source CvP Driver in Linux Systems
      • Downstream Open Source CvP Driver
  • Added .sof file conditions to CvP Limitations.
  • Updated image and descriptions to reflect six tiles instead of four in CvP System.
2022.05.24 21.4 Removed note about periphery image loading time and configuration from the Power-Up Sequence Timing in CvP Initialization Mode table.
2022.03.02 21.4
  • Updated the CvP System section. The option to enable either lower or upper PCIe Hard block CvP support is enabled in the PCIe Hard IP.
  • Added note for timing sequence i in the Power-Up Sequence Timing in CvP Initialization Mode table.
2021.12.13 21.4 Made the following change:
  • Added conditions used to validate the power-up sequence timing in PCIe® Wake-Up Time Requirement: For CvP Initialization Mode
2021.10.04 21.3 Made the following changes:
  • Revised CvP Support for Agilex™ 7 Device Family table:
    • Added preliminary tag to the R-tile and F-tile content
    • Added note describing the REFCLK_GXP clock behavior in R-tile
  • Added 100ms PCIe® link up time requirement in CvP Initialization Mode.
  • Updated link for Download the OpenSource Linux CvP Downstream Driver in Generating the Synthesis HDL files for Altera™ FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe® Express.
  • Added Implementation of CvP Update Mode section and all related subsections.
2021.07.01 21.2
Sections Updated:
  • CvP Modes [CvP Support for Intel Agilex Device Family Table updated
  • Configuration Images [Periphery image and core image definitions updated]
  • CvP Driver Flow [CvP Driver Flow Flowchart updated]
  • Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express [Enable CVP information added in Step 7]
  • Setting up the CvP Parameters in Device and Pin Options [Step 2b updated]
  • Downstream open source CvP Driver [This is a new section]
  • Upstream open source CvP Driver [This is a new section]
  • Programming CvP Images [Step 7 and Step 8 updated]
2021.03.24 20.4
Sections Updated:
  • CvP Modes
  • CvP System
2020.12.14 20.4 Removed the SDM_IO15 pin documented in Table: CvP Pin Descriptions and Connection Guidelines.
2020.09.15 19.4
  • Added information about the supported tile in Table: CvP Support for Agilex™ 7 Device Family.
  • Updated following figure and table in section For CvP Initialization Mode:
    • Figure: PCIe Timing Sequence in CvP Initialization Mode
    • Table: Power-Up Sequence Timing in CvP Initialization Mode
2020.01.07 19.4 Initial release.