| Bits | Name | Reset Value | Access | Description |
|---|---|---|---|---|
| [15:11] | — | Variable | RO | Reserved. |
| [10] | CVP_CONFIG_SUCCESS | Variable | RO | Status bit set by the device to indicate that the core image configuration was successful. |
| [9] | — | Variable | RO | Reserved. |
| [8] | PLD_CLK_IN_USE | Variable | RO |
From clock switch module to fabric. You can use this bit for debug. |
| [7] | CVP_CONFIG_DONE | Variable | RO |
Indicates that the device has completed the device configuration via CvP and there were no errors. |
| [6] | — | Variable | RO | Reserved. |
| [5] | USERMODE | Variable | RO | Indicates if the configurable FPGA fabric is in user mode. |
| [4] | CVP_EN | Variable | RO | Indicates if the device has enabled CvP mode. |
| [3] | CVP_CONFIG_ERROR | Variable | RO | Reflects the value of this signal from the device, checked by software to determine if there was an error during configuration. |
| [2] | CVP_CONFIG_READY | 0x0 | RO |
Reflects the value of this signal from the device, checked by software during programming algorithm to determine the device is ready for configuration. |
| [1:0] | — | Variable | RO | Reserved. |