5.3.6. CvP Mode Control Register

Table 10. CvP Mode Control Register (Byte Offset: 0xD20)
Bits	Name	Reset Value	Access	Description
[31:3]	—	0x0000	RO	Reserved.
[2]	—	0x0000	RW	Reserved³.
[1]	PLD_DISABLE	1'b0	RW/RO	Enables/disables the PLD interface. This allows Host driver to switch the PLD interface out before USER MODE deasserts, and to switch the PLD interface back in only after USER MODE has been asserted. This helps to prevent any glitches or race conditions during the USER MODE switching. 1: Disable the application layer interface. 0: Enable the application layer interface. Only change the value of this signal when there has been no other TLP’s to or from the HIP for 10 us. There should be no TLP’s issued to the HIP for 10 us after this value changes. When entering CVP, this bit should be set before CVP_MODE is set. When exiting CVP, it should be cleared after CVP_MODE is clears. This ensures that there is no PLD switching during CVP. This field is RW when cvp_en=1, and RO when cvp_en=0.
[0]	CVP_MODE	1'b0	RW	Controls whether the Hard IP for PCI Express is in CVP_MODE or normal mode. 1: CVP_MODE is active. Signals to the SDM active and all TLPs are route to the Configuration Space. This CVP_MODE cannot be enabled if CVP_EN = 0. 0: The IP core is in normal mode and TLPs are route to the FPGA fabric.

³ Altera™ recommends to set the reserved bit to 0 for write operation. For read operations, the PCIe^® IP always generates 0 as the output.

5.3.6. CvP Mode Control Register - 2025-12-16