5. CvP Driver and Registers - 2025-12-16

Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

Version: 23.1

1. Overview
1.1. Benefits of Using CvP
1.2. CvP System
1.3. CvP Modes
1.3.1. CvP Limitations
1.3.1.1. CvP Error Recovery
2. CvP Description
2.1. Configuration Images
2.2. CvP Modes
2.2.1. CvP Initialization Mode
2.2.2. CvP Update Mode
2.3. Compression Features
2.4. Pin Description
3. CvP Topologies
3.1. Single Endpoint
3.2. Multiple Endpoints
4. Design Considerations
4.1. Designing CvP for an Open System
4.1.1. FPGA Power Supplies Ramp Time Requirement
4.1.2. PCIe Wake-Up Time Requirement
4.1.2.1. For CvP Initialization Mode
4.1.2.2. For CvP Update Mode
4.2. Designing CvP for a Closed System
5. CvP Driver and Registers
5.1. CvP Driver Support
5.2. CvP Driver Flow
5.3. VSEC Registers for CvP
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Altera Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 7 FPGAs
6.1. Implementation of CvP Initialization Mode
6.1.1. Generating the Synthesis HDL Files
6.1.2. Setting up the CvP Parameters in Device and Pin Options
6.1.3. Compiling the Design
6.1.4. Converting the SOF File
6.1.5. Bringing up the Hardware
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems
6.1.5.2. Setting Up the Correct MSEL Switch State
6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode
6.2.1. Instantiating the PCIe Hard IP
6.2.2. Setting Up the CvP Parameters
6.2.3. Setting Up the Base Revision
6.2.3.1. Creating a Reserved Core Partition
6.2.3.2. Defining a Logic Lock Region
6.2.3.3. Compiling and Exporting the Root Partition
6.2.4. Setting Up and Compile the Updated Revision
6.2.5. Converting the SOF File
6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
7. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

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