The CvP configuration scheme has the following advantages:
- Reduces system costs by reducing the size of the local flash device that stores the configuration data.
- Allows update of the FPGA without reprogramming the flash.
- Enables dynamic core updates without requiring a system power down. CvP allows you to update the FPGA core fabric through the PCIe® link without a host restart or FPGA full chip reinitialization.
- Provides a simpler software model for configuration. A smart host can use the PCIe® protocol and the application topology to initialize and update the FPGA core fabric.
- Allows quick update of your design for changing application loads.