ALTDQ_DQS2 IP Core User Guide - Describes the design and configuration of the ALTDQ_DQS2 IP core. - 2017-05-08

Version: 17.0

ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 Features
ALTDQ_DQS2 Device Support
Resource Utilization and Performance
ALTDQ_DQS2 Parameter Settings
ALTDQ_DQS2 Data Paths
DQ and DQS Input Path
DQ and DQS Input Paths for Stratix V Devices
Data Input Path for Arria V, Cyclone V, and Stratix V Devices
Blocks in DQ and DQS Data Input Path
DQS Logic
Capture DDIO to Read FIFO Path
FIFO Control
DQ and DQS Output Path
DQ and DQS Output Path for Stratix V Devices
Blocks in DQ and DQS Output Path
DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports
ALTDQ_DQS2 Data Strobe Ports
ALTDQ_DQS2 Data Ports
ALTDQ_DQS2 Termination Control Ports
ALTDQ_DQS2 PLL and DLL Ports
ALTDQ_DQS2 Hard FIFO Ports
ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example
Instantiating ALTDQ_DQS2 IP Core
Instantiating the ALTDLL IP Core
Instantiating ALT_OCT IP Core
Instantiating Altera PLL
Altera PLL Clock Settings Information
Setting Up NativeLink and Simulation Settings
Understanding Simulation Results—Stratix V Design Example
Dynamic Configuration
DQS Write Operation
Side Read Operation
Side Write Operation
DQS Read Operation
DQS Delay Chain
Hard Read FIFO
Simulation Results
SDC Walkthrough
Analyzing Same Edge Transfer
Constraining Outgoing DQS Strobe
Arria V Design Example
Instantiating the ALTDQ_DQS2 IP Core
Instantiating the ALTDLL IP Core
Instantiating ALT_OCT IP Core
Instantiating Altera PLL
Altera PLL Clock Settings Information
Setting Up NativeLink and Simulation Settings
Understanding Simulation Results—Arria V Design Example
Dynamic Configuration
DQS Write Operation
Side Read Operation
Side Write Operation
DQS Read Operation
DQS Delay Chain
VFIFO, LFIFO, and Read FIFO
DQS Enable Control
Simulation Results
SDC Walkthrough
Analyzing Same Edge Transfer
Constraining Outgoing DQS Strobe
Timing Violation
tq_analysis.tcl
IP-Generate Command
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide Archives
Document Revision History

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