Arria V Avalon-ST Interface for PCIe Solutions User Guide - Hard IP for PCI Express Endpoint and Root Port, Gen1, Gen2 - 2023-01-04

Version: 18.0

1. Datasheet
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.8.1. Compatibility Testing Environment
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
2. Getting Started with the Arria V Hard IP for PCI Express
2.1. Qsys Design Flow
2.1.1. Generating the Testbench
2.1.2. Simulating the Example Design
2.1.3. Generating Synthesis Files
2.1.4. Understanding the Files Generated
2.1.5. Understanding Physical Placement of the PCIe IP Core
2.1.6. Compiling the Design in the Quartus Prime Software
2.2. Modifying the Example Design
2.3. Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component
3. Parameter Settings
3.1. Avalon-ST System Settings
3.2. Link Capabilities
3.3. Port Function Parameters Shared Across All Port Functions
3.3.1. Device Capabilities
3.3.2. Error Reporting
3.3.3. Link Capabilities
3.3.4. Slot Capabilities
3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions
3.4.1. Base Address Register (BAR) and Expansion ROM Settings
3.4.2. Base and Limit Registers for Root Ports
3.4.3. Device Identification Registers for Function <n>
3.4.4. Func <n> Device
3.4.5. Func <n> Link
3.4.6. Func <n> MSI and MSI-X Capabilities
3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.1.1. Avalon‑ST RX Interface
4.1.1.1. Avalon-ST RX Component Specific Signals
4.1.1.2. Data Alignment and Timing for the 64‑Bit Avalon -ST RX Interface
4.1.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
4.1.2. Avalon-ST TX Interface
4.1.2.1. Avalon-ST Packets to PCI Express TLPs
4.1.2.2. Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface
4.1.2.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
4.1.2.4. Root Port Mode Configuration Requests
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.10.1. Configuration Space Register Access Timing
4.10.2. Configuration Space Register Access
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
4.13.1. Transceiver Reconfiguration
4.13.2. Serial Interface Signals
4.13.2.1. Physical Layout of Hard IP in Arria V Devices
4.13.2.2. Channel Placement in Arria V Devices
4.13.3. Hard IP Reconfiguration Interface
4.13.4. PIPE Interface Signals
4.13.5. Test Signals
5. Registers
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
6. Reset and Clocks
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
6.2. Clocks
6.2.1. Clock Domains
6.2.1.1. pclk
6.2.1.2. coreclkout_hip
6.2.1.3. pld_clk
6.2.2. Clock Summary
7. Interrupts
7.1. Interrupts for Endpoints
7.1.1. MSI Interrupts
7.1.2. MSI-X
7.1.3. Implementing MSI-X Interrupts
7.1.3.1. Legacy Interrupts
7.1.3.1.1. Enabling MSI or Legacy Interrupts
7.2. Interrupts for Root Ports
8. Error Handling
8.1. Physical Layer Errors
8.2. Data Link Layer Errors
8.3. Transaction Layer Errors
8.4. Error Reporting and Data Poisoning
8.5. Uncorrectable and Correctable Error Status Bits
9. IP Core Architecture
9.1. Top-Level Interfaces
9.1.1. Avalon-ST Interface
9.1.2. Clocks and Reset
9.1.3. Local Management Interface (LMI Interface)
9.1.4. Hard IP Reconfiguration
9.1.5. Transceiver Reconfiguration
9.1.6. Interrupts
9.1.7. PIPE
9.2. Transaction Layer
9.2.1. Configuration Space
9.3. Data Link Layer
9.4. Physical Layer
9.5. Multi-Function Support
10. Transaction Layer Protocol (TLP) Details
10.1. Supported Message Types
10.1.1. INTX Messages
10.1.2. Power Management Messages
10.1.3. Error Signaling Messages
10.1.4. Locked Transaction Message
10.1.5. Slot Power Limit Message
10.1.6. Vendor-Defined Messages
10.1.7. Hot Plug Messages
10.2. Transaction Layer Routing Rules
10.3. Receive Buffer Reordering
10.3.1. Using Relaxed Ordering
11. Throughput Optimization
11.1. Throughput of Posted Writes
11.2. Throughput of Non-Posted Reads
12. Design Implementation
12.1. Making Analog QSF Assignments Using the Assignment Editor
12.2. Making Pin Assignments
12.3. Recommended Reset Sequence to Avoid Link Training Issues
13. Additional Features
13.1. Configuration over Protocol (CvP)
13.2. Autonomous Mode
13.2.1. Enabling Autonomous Mode
13.2.2. Enabling CvP Initialization
13.3. ECRC
13.3.1. ECRC on the RX Path
13.3.2. ECRC on the TX Path
14. Hard IP Reconfiguration
15. Transceiver PHY IP Reconfiguration
15.1. Connecting the Transceiver Reconfiguration Controller IP Core
15.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
16. Testbench and Design Example
16.1. Endpoint Testbench
16.1.1. Endpoint Testbench for SR-IOV
16.2. Root Port Testbench
16.3. Test Driver Module
16.4. Root Port Design Example
16.5. Root Port BFM Overview
16.5.1. BFM Memory Map
16.5.2. Configuration Space Bus and Device Numbering
16.5.3. Configuration of Root Port and Endpoint
16.5.4. Issuing Read and Write Transactions to the Application Layer
16.6. BFM Procedures and Functions
16.6.1. ebfm_barwr Procedure
16.6.2. ebfm_barwr_imm Procedure
16.6.3. ebfm_barrd_wait Procedure
16.6.4. ebfm_barrd_nowt Procedure
16.6.5. ebfm_cfgwr_imm_wait Procedure
16.6.6. ebfm_cfgwr_imm_nowt Procedure
16.6.7. ebfm_cfgrd_wait Procedure
16.6.8. ebfm_cfgrd_nowt Procedure
16.6.9. BFM Configuration Procedures
16.6.9.1. ebfm_cfg_rp_ep Procedure
16.6.9.2. ebfm_cfg_decode_bar Procedure
16.6.10. BFM Shared Memory Access Procedures
16.6.10.1. Shared Memory Constants
16.6.10.2. shmem_write Task
16.6.10.3. shmem_read Function
16.6.10.4. shmem_display Verilog HDL Function
16.6.10.5. shmem_fill Procedure
16.6.10.6. shmem_chk_ok Function
16.6.11. BFM Log and Message Procedures
16.6.11.1. ebfm_display Verilog HDL Function
16.6.11.2. ebfm_log_stop_sim Verilog HDL Function
16.6.11.3. ebfm_log_set_suppressed_msg_mask Task
16.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
16.6.11.5. ebfm_log_open Verilog HDL Function
16.6.11.6. ebfm_log_close Verilog HDL Function
16.6.12. Verilog HDL Formatting Functions
16.6.12.1. himage1
16.6.12.2. himage2
16.6.12.3. himage4
16.6.12.4. himage8
16.6.12.5. himage16
16.6.12.6. dimage1
16.6.12.7. dimage2
16.6.12.8. dimage3
16.6.12.9. dimage4
16.6.12.10. dimage5
16.6.12.11. dimage6
16.6.12.12. dimage7
16.7. Setting Up Simulation
16.7.1. Changing Between Serial and PIPE Simulation
16.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
16.7.3. Viewing the Important PIPE Interface Signals
16.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
16.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
16.7.6. Changing between the Hard and Soft Reset Controller
17. Debugging
17.1. Hardware Bring-Up Issues
17.2. Link Training
17.2.1. Link Hangs in L0 State
17.3. Use Third-Party PCIe Analyzer
17.4. BIOS Enumeration Issues
A. Transaction Layer Packet (TLP) Header Formats
A.1. TLP Packet Formats without Data Payload
A.2. TLP Packet Formats with Data Payload
B. Lane Initialization and Reversal
C. Document Revision History
C.1. Document Revision History of the Arria V Avalon Streaming (Avalon-ST) Interface for PCIe Solutions User Guide

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