ALTPLL (Phase-Locked Loop) IP Core User Guide - Describes the implementation of the phase lock loop (PLL) circuitry. - 2017-06-16

Version: 17.0

ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL Features
Phase-Locked Loop
Building Blocks of a PLL
PLL Behavior
Types of PLLs
Parameter Setting
Total Number of PLL Available in Each Supported Device Family
Operation Modes
Operation Modes Supported in Each Device Family
Parameter Settings
Determining the PLL Lock Range
Expanding the PLL Lock Range
Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing
Simulating External Feedback Board Delay
Output Clocks
Parameter Settings
Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled
Summary of PLL Output Clocks
Advanced Features
Advanced Control Signals (pllena, areset, pfdena)
pllena
areset
pfdena
Parameter Settings
Summary of Advanced Control Signals
Clock Switchover
Parameter Settings
Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking
Parameter Settings
Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset
Gated Lock
Self-Reset on Loss of Lock
Parameter Settings
Calculating the Value of Gated Lock Counter
Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth
Parameter Settings
Summary of Programmable Bandwidth Support
Advanced PLL Parameters
Advanced Parameter Settings
PLL Dynamic Reconfiguration
Parameter Settings
Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration
Supported Devices
Parameter Settings
Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
PLL Output Counter Cascading
Ports and Parameters
ALTPLL Input Ports
ALTPLL Output Ports
ALTPLL Bidirectional Port
ALTPLL Parameters
Design Examples
Design Files
Design Example 1: Differential Clock
Generating a 166-MHz Differential SSTL External Clock
Implementing the ddr_clk Design
Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks
Implementing the shift_clk Design
Simulating the shift_clk Design in the ModelSim-Altera Software
Document Revision History

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