Stratix 10 GX/SX Device Overview - Stratix 10 GX FPGAs and SX SoCs deliver 2X the core performance and up to 70% lower power over previous generation high-performance FPGAs. - 2024-06-28

1. Stratix 10 GX/SX Device Overview
1.1. Stratix 10 GX/SX Family Variants
1.1.1. Available Options
1.2. Innovations in Stratix 10 FPGAs and SoCs
1.3. FPGA and SoC Features Summary
1.4. Stratix 10 Block Diagram
1.5. Stratix 10 FPGA and SoC Family Plan
1.6. Hyperflex Core Architecture
1.7. Heterogeneous 3D SiP Transceiver Tiles
1.8. Stratix 10 Transceivers
1.8.1. PMA Features
1.8.2. PCS Features
1.9. PCI Express Gen1/Gen2/Gen3 Hard IP
1.10. Interlaken PCS Hard IP
1.11. 10G Ethernet Hard IP
1.12. External Memory and General Purpose I/O
1.13. Adaptive Logic Module (ALM)
1.14. Core Clocking
1.15. Fractional Synthesis PLLs and I/O PLLs
1.16. Internal Embedded Memory
1.17. Variable Precision DSP Block
1.18. Hard Processor System (HPS)
1.18.1. Key Features of the Stratix 10 HPS
1.19. Power Management
1.20. Device Configuration and Secure Device Manager (SDM)
1.21. Device Security
1.22. Configuration via Protocol Using PCI Express
1.23. Partial and Dynamic Reconfiguration
1.24. Fast Forward Compile
1.25. Single Event Upset (SEU) Error Detection and Correction
1.26. Document Revision History for the Stratix 10 GX/SX Device Overview

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