E-Tile Transceiver PHY User Guide - E-tile transceivers have up to 24 GXE channels per tile, with maximum transceiver data rates of up to 28.9 Gbps for NRZ and 57.8 Gbps for pulse amplitude modulation (PAM4), and support 10G/25G/100G Ethernet Hard IP and Reed Solomon Forward Error Correction (RS-FEC) protocols. - 2026-04-09
Product Type
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Stratix Families > Stratix 10
Device Families > Agilex Families > Agilex 7
Device Families > Stratix Families
Resource Type
Documentation > User Guides
Source Name
DITA
1. E-Tile Transceiver PHY Overview
1.1. Supported Features
1.2. E-Tile Layout in Stratix 10 Device Variants
1.2.1. Stratix 10 TX H-Tile and E-Tile Configurations
1.2.2. Stratix 10 MX H-Tile and E-Tile Configurations
1.2.3. Stratix 10 DX P-Tile and E-Tile Configurations
1.3. E-Tile Layout in Agilex™ 7 F-Series Device Variants
1.4. Transceiver Counts
1.5. E-Tile Building Blocks
1.5.1. GXE Transceiver Channel
1.5.2. GXE Channel Usage
1.5.3. Reference Clocks
1.5.4. Ethernet Hard IP (EHIP)
1.5.5. Supported Applications/Modes
1.5.6. Feature Comparison Between Transceiver Tiles
1.6. E-Tile Transceiver PHY Overview Revision History
2. Implementing the Transceiver PHY Layer
2.1. Transceiver Design Flow in the Native PHY IP Core
2.1.1. E-Tile Native PHY IP Core
2.2. Configuring the Native PHY IP Core
2.2.1. General and Datapath Parameters
2.2.2. PMA Parameters
2.2.2.1. TX PMA Options
2.2.2.2. TX PMA Pre-equalization
2.2.2.3. RX PMA Options
2.2.2.4. RX PMA Optional Ports
2.2.3. Core Interface Options
2.2.3.1. Core Interface Parameters
2.2.3.2. TX Clock Options
2.2.3.3. RX Clock Options
2.2.3.4. Latency Measurement Options
2.2.4. PMA Interface
2.2.4.1. PMA Interface Options
2.2.4.2. Gearbox 64/66
2.2.5. PMA Adaptation Parameters
2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters
2.2.6.1. Fibre-Channel and CPRI Modes
2.2.6.2. 128 GFC Mode
2.2.6.3. 25 GbE FEC Direct Mode
2.2.6.4. Interlaken Mode
2.2.7. Reset Parameters
2.2.8. Dynamic Reconfiguration Parameters
2.2.9. Deskew Logic
2.2.10. Port Information
2.2.11. PLL Mode
2.2.12. Simplex Support
2.3. Implementing the Transceiver PHY Layer Revision History
3. E-Tile Transceiver PHY Architecture
3.1. Physical Medium Attachment (PMA) Architecture
3.1.1. Transmitter PMA
3.1.1.1. High Speed Differential Transmitter
3.1.1.1.1. High Speed Transmitter Line Buffer
3.1.1.1.2. TX Equalizer
3.1.1.2. Gray Encoder/Precoder
3.1.1.3. Serializer
3.1.1.4. Data Pattern Generation
3.1.2. Receiver PMA
3.1.2.1. Receiver Buffer
3.1.2.1.1. Programmable Termination Modes
3.1.2.1.2. RX Adaptation Modes
3.1.2.2. Clock Data Recovery (CDR) Block
3.1.2.3. Input Sampler
3.1.2.4. Deserializer
3.1.2.5. Data Pattern Verifier
3.1.3. PMA Tuning
3.1.3.1. Purpose of PMA Tuning
3.1.3.2. PMA Bring Up Flow
3.1.3.3. PMA Tuning Guidelines
3.1.3.4. General PMA Tuning Guidelines
3.1.4. Duplex Adaptation Flow
3.1.5. RX Simplex Adaptation Flow
3.1.6. Dynamic Reconfiguration Adaptation Flow
3.1.7. Loopback modes
3.1.7.1. Internal Serial Loopback Path
3.1.7.2. Reverse Parallel Loopback Path
3.1.8. PMA Interface
3.1.9. TX PMA Bonding
3.1.9.1. Transceiver Interface Deskew Logic
3.1.9.2. Dedicated Balanced PLL Reference Clock Tree
3.1.10. Unused Transceiver Channels
3.1.10.1. Unused Transceiver Channels in a Used Tile
3.1.10.2. Unused Transceiver Channels in Completely Unused Tiles
3.1.10.3. Unused Transceiver Channels in High-Speed PAM4 Mode
3.1.10.4. Reconfiguring from Mission Mode to Channel Protection Mode
3.1.10.5. Reconfiguring from Channel Protection Mode to Mission Mode
3.1.11. Low Power Mode (LPM)
3.2. Physical Coding Sublayer (PCS) Architecture
3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture
3.3.1. RS-FEC Modes
3.4. E-Tile Transceiver PHY Architecture Revision History
4. Clock Network
4.1. Reference Clock Pins
4.1.1. QSF Assignments for Reference Clock Pins
4.1.2. Dynamic Reconfiguration of Reference Clock
4.2. Core Clock Network Use Case
4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block
4.2.2. Single 10 Gbps PMA Direct Channel (without FEC)
4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block
4.2.3.1. Master-Slave Configuration: Option 1
4.2.3.2. Master-Slave Configuration: Option 2
4.2.4. PMA Direct 25 Gbps x 4 (FEC Off)
4.2.5. PMA Direct 10.3125 Gbps x 4
4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4) (FEC On)
4.2.7. PMA Direct 100GE PAM4 (50 Gbps x 2) (Aggregate FEC On)
4.2.8. PMA Direct High Data Rate (FEC Off)
4.3. Clock Network Revision History
5. PMA Calibration
5.1. PMA Calibration Revision History
6. Resetting Transceiver Channels
6.1. When Is Reset Required?
6.2. How Do I Reset?
6.2.1. Disabling the E-Tile Transceiver
6.2.2. Selecting the Reset Controller's Clock Source
6.3. Reset Block Architecture
6.4. PMA Analog Reset
6.5. High Level Specification
6.5.1. Automatic Reset Mode
6.5.2. Manual Reset Mode
6.5.3. Reset Controller Bypass
6.5.3.1. Reset Controller Bypass Ports
6.5.3.2. Reset Controller Bypass Reset Procedure
6.6. Master-Slave Clocking Option 2 Reset Details
6.7. Quartus Prime Instantiated Transceiver Reset Sequencer
6.8. Block Diagrams
6.9. Interfaces
6.9.1. Reset Parameters in the Native PHY GUI
6.9.2. HDL Ports/Interfaces
6.10. Resetting Transceiver Channels Revision History
7. Dynamic Reconfiguration
7.1. Dynamically Reconfiguring Channel Blocks
7.2. Dynamic Reconfiguration Maximum Data Rate Switch
7.3. Interacting with the Dynamic Reconfiguration Interface
7.4. Unsupported Features
7.5. Reading from the Dynamic Reconfiguration Interface
7.6. Writing to the Dynamic Reconfiguration Interface
7.7. Multiple Reconfiguration Profiles
7.7.1. Reconfiguration Files
7.7.2. Embedded Reconfiguration Streamer
7.7.2.1. Register 0x40140
7.7.2.2. Register 0x40141
7.8. Arbitration
7.9. Recommendations for PMA Dynamic Reconfiguration
7.10. Steps to Perform Dynamic Reconfiguration
7.11. PMA Attribute Details
7.12. Dynamic Reconfiguration Flow for Special Cases
7.12.1. Switching Reference Clocks
7.12.1.1. Switching Between Any Two refclk[0, 1, 2, 3, 4, 5, 6, 7] Reference Clocks or Changing the Reference Clock Frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8]
7.12.1.2. Switching from/to refclk[0, 1, 2, 3, 4, 5, 6, 7] to/from refclk[8]
7.12.1.3. Changing the refclk[1] Reference Clock Frequency
7.12.2. Reconfiguring PMA Settings
7.13. Ports and Parameters
7.14. Embedded Debug Features
7.14.1. Native PHY Debug Master Endpoint (NPDME)
7.14.2. Optional Dynamic Reconfiguration Logic
7.14.2.1. Capability Registers
7.14.2.2. Control and Status Registers
7.15. Timing Closure Recommendations
7.16. Transceiver Register Map
7.17. Loading IP Configuration Settings
7.17.1. Loading IP Configuration Settings Process
7.17.2. Alternative Method for Setting PMA Attributes
7.18. Dynamic Reconfiguration Revision History
8. Dynamic Reconfiguration Examples
8.1. Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode
8.2. PRBS Usage Model
8.3. PMA Error Injection
8.4. PMA Receiver Equalization Adaptation Usage Model
8.5. User-Defined Pattern Example
8.6. Configuring the Attenuation Value (VOD)
8.7. Configuring the Post Emphasis Value
8.8. Configuring pretap1 Values
8.9. Inverting TX Polarity for the PMA Driver
8.10. Inverting RX Polarity for the PMA Driver
8.11. Configuring a PMA Parameter Tunable by the Adaptive Engine
8.12. Configuring a PMA Parameter Using Native PHY IP
8.12.1. PMA Bring Up Flow Using Native PHY IP
8.12.2. Native PHY IP GUI Details
8.12.3. Loading a PMA Configuration
8.13. Enabling Low Power Mode for Multiple Channels
8.14. Initializing an RX
8.15. Resetting the RX Equalization
8.16. Dynamic Reconfiguration Examples Revision History
9. Register Map
9.1. PMA Register Map
9.1.1. PMA Capability Registers
9.1.2. PMA Control and Status Registers
9.1.3. PMA Avalon Memory-Mapped Interface
9.2. PMA Attribute Codes
9.2.1. 0x0001: PMA Enable/Disable
9.2.2. 0x0002: PMA PRBS Settings
9.2.3. 0x0003: Data Comparison Set Up and Start/Stop
9.2.4. 0x0005: TX Channel Divide By Ratio
9.2.5. 0x0006: RX Channel Divide By Ratio
9.2.6. 0x0008: Internal Serial Loopback and Reverse Parallel Loopback Control
9.2.7. 0x000A: Receiver Tuning Controls
9.2.8. 0x000E: RX Phase Slip
9.2.9. 0x0011: PMA TX/RX Calibration
9.2.10. 0x0013: TX/RX Polarity and Gray Code Encoding
9.2.11. 0x0014: TX/RX Width Mode
9.2.12. 0x0015: TX Equalization
9.2.13. 0x0017: Error Counter Reset
9.2.14. 0x0018: Status/Debug Register
9.2.15. 0x0019: Status/Debug Register Next Write Field
9.2.16. 0x001A: Status/Debug Register Next Read Field
9.2.17. 0x001B: TX Error Injection Signal
9.2.18. 0x001C: Incoming RX Data Capture
9.2.19. 0x001E: Error Count Status
9.2.20. 0x0020: Electrical Idle Detector
9.2.21. 0x002B: RX Termination and TX Driver Tri-state Behavior
9.2.22. 0x0030: PMA Mux Clock Swap
9.2.23. 0x0126: Read Receiver Tuning Parameters
9.2.24. Reading and Writing PMA Analog Parameters Using Attributes
9.2.24.1. Reading PMA Analog Parameters
9.2.24.2. Updating PMA Analog Parameters
9.2.24.3. Loading Parameters into the Receiver
9.2.24.4. Fixing Parameter Values
9.2.24.5. Reading NRZ/PAM4 Eye Height
9.2.24.6. Enabling and Disabling Electrical Idle Detector Filtering and Reading Electrical Idle Detector Status
9.2.24.7. Initial Adaptation Effort Levels
9.3. PMA Registers 0x200 to 0x203 Usage
9.3.1. PMA Analog Reset
9.3.2. Set PRBS Mode and Internal Serial Loopback
9.3.3. Use Cases for Opcode START_ADAPTATION
9.3.4. Read the Physical Channel Number
9.3.5. Check the PMA Adaptation Status
9.3.6. Load a PMA Configuration using Opcode LOAD_PMA_CONFIGURATION
9.4. Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006
9.5. RS-FEC Registers
9.5.1. rsfec_top_clk_cfg
9.5.2. rsfec_top_tx_cfg
9.5.3. rsfec_top_rx_cfg
9.5.4. tx_aib_dsk_conf
9.5.5. rsfec_core_cfg
9.5.6. rsfec_lane_cfg
9.5.7. tx_aib_dsk_status
9.5.8. rsfec_debug_cfg
9.5.9. rsfec_lane_tx_stat
9.5.10. rsfec_lane_tx_hold
9.5.11. rsfec_lane_tx_inten
9.5.12. rsfec_lane_rx_stat
9.5.13. rsfec_lane_rx_hold
9.5.14. rsfec_lane_rx_inten
9.5.15. rsfec_lanes_rx_stat
9.5.16. rsfec_lanes_rx_hold
9.5.17. rsfec_lanes_rx_inten
9.5.18. rsfec_ln_mapping_rx
9.5.19. rsfec_ln_skew_rx
9.5.20. rsfec_cw_pos_rx
9.5.21. rsfec_core_ecc_hold
9.5.22. rsfec_err_inj_tx
9.5.23. rsfec_err_val_tx
9.5.24. rsfec_corr_cw_cnt (Low)
9.5.25. rsfec_corr_cw_cnt (High)
9.5.26. rsfec_uncorr_cw_cnt (Low)
9.5.27. rsfec_uncorr_cw_cnt (High)
9.5.28. rsfec_corr_syms_cnt (Low)
9.5.29. rsfec_corr_syms_cnt (High)
9.5.30. rsfec_corr_0s_cnt (Low)
9.5.31. rsfec_corr_0s_cnt (High)
9.5.32. rsfec_corr_1s_cnt (Low)
9.5.33. rsfec_corr_1s_cnt (High)
9.6. Register Map Revision History
10. Debugging E-Tile Transceiver Links
10.1. E-Tile Transceiver Toolkit Overview
10.2. E-Tile Transceiver Debugging Flow Walkthrough
10.3. Modifying the Design to Enable E-Tile Transceiver Debug
10.3.1. Debug Parameters for the E-Tile Transceiver IP in the Parameter Editor
10.3.2. Debug Parameters for Stratix 10 E-Tile Transceiver Native PHY IP in the Parameter Editor
10.3.3. Instantiating and Parameterizing E-Tile Transceiver IP
10.4. Programming the Design into an Altera FPGA
10.5. Loading the Design in the E-Tile Transceiver Toolkit
10.6. Verifying E-Tile Hardware Connections
10.7. Running Transceiver Tests
10.7.1. Running BER Tests
10.7.2. Link Optimization Tests
10.7.3. Running Eye Viewer Tests
10.8. Controlling PMA Analog Settings
10.9. Debugging E-Tile Transceiver Links Revision History
A. E-Tile Channel Placement Tool
A.1. E-Tile Channel Placement Tool Revision History
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
B.1. Building Blocks and Considerations
B.2. Starting a New Quartus Prime Pro Edition Design
B.3. Selecting the Configuration Clock Source
B.4. Instantiating the Transceiver Native PHY IP
B.5. Instantiating the In-system Sources and Probes Altera FPGA IP
B.6. Making the Top Level Connection
B.7. Assigning Pins
B.8. Bringing up the Board
B.9. Debug Tools
B.9.1. Monitoring Transceiver Signals
B.10. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation Revision History
C. Signal Detect Algorithm
C.1. Signal Detect Algorithm Revision History
D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode
D.1. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode Revision History
E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode
E.1. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode Revision History
F. Hold Timing Violation
F.1. Hold Timing Violation Revision History