PHY Lite for Parallel Interfaces FPGA IP User Guide - This user guide describes the functional description, steps to generate, and guidelines to design the PHY Lite for Parallel Interfaces FPGA IP in Agilex 5 D-Series, E-Series, Agilex 7 F-Series, I-Series, and M-Series, Stratix 10 , Arria 10 , and Cyclone 10 GX devices. - 2026-02-28

Version

25.3.1

Product Type

Device Families > Agilex Families > Agilex 5

Device Families > Agilex Families > Agilex 5 > D-Series

Device Families > Agilex Families > Agilex 7 > M-Series

Device Families > Agilex Families > Agilex 5 > E-Series

Device Families > Arria Families > Arria 10

Device Families > Agilex Families

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Stratix Families > Stratix 10

Device Families > Agilex Families > Agilex 7

Device Families > Cyclone Families

Device Families > Arria Families

Device Families > Stratix Families

Device Families > Agilex Families > Agilex 7 > I-Series

Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX

Device Families > Cyclone Families > Cyclone 10

Resource Type

Documentation > User Guides

Source Name

DITA