PHY Lite for Parallel Interfaces FPGA IP User Guide - This user guide describes the functional description, steps to generate, and guidelines to design the PHY Lite for Parallel Interfaces Intel® FPGA IP in Agilex™ 5 E-Series, Agilex™ 7 F-Series, I-Series, and M-Series, Stratix® 10, Arria® 10, and Cyclone® 10 GX devices. - 2025-02-10

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24.3.1