Cyclone V SoC Power Optimization - 2015-02-09

1. Cyclone V SoC Power Optimization
1.1. Power Reduction
1.2. HPS Power Reduction Methods
1.2.1. MPU
1.2.1.1. HPS Method 1: Fit Code in Cache
1.2.1.2. HPS Method 2: Processor Standby Modes and Dynamic Clock Gating
1.2.1.3. HPS Method 3: CPU1 in WFI/WFE or Standby Loop
1.2.1.4. HPS Method 4: Lowering CPU Frequency
1.2.2. Peripherals
1.2.2.1. HPS Method 5: Energy Efficient Ethernet
1.2.2.2. HPS Method 6: USB Power Management
1.2.2.3. HPS Method 7: Unused Peripherals in Reset
1.2.3. HPS Power Reduction Summary
1.3. FPGA Power Reduction Methods
1.3.1. FPGA Power Consumption
1.3.2. FPGA Portion Power Down
1.3.3. FPGA Power Off Step 1: Board Design (Power Rail) Choices
1.3.4. FPGA Power Off Step 2: Quiet FPGA
1.3.5. FPGA Power Off Step 3: Power Off the FPGA
1.3.6. FPGA Power Off Step 4: Wake up Event for Power on and FPGA Configuration
1.3.7. FPGA Power Off Step 5: Power On and FPGA Reconfiguration Time Considerations
1.4. Power Optimization Summary
1.5. Appendix: Power Measurement Techniques for Cyclone V SoC Dev Kit
1.5.1. Power Monitoring and Measurement
1.5.2. Cyclone V SoC Development Kit Power Management ICs
1.5.3. Cyclone V SoC Development Kit Power Monitor Application
1.5.3.1. Starting the Application
1.5.3.2. Windows Instructions
1.5.3.3. Linux Instructions
1.5.4. LTC LTpower Play Tool
1.5.4.1. Requirements
1.5.4.2. LTC Video Tutorial
1.5.5. Using the LTC2978A Linux Driver
1.5.5.1. Compiling the Driver
1.5.5.2. Using the Driver
1.5.6. Power Measurement Results on Cyclone V SoC Development Kit
1.5.7. Document Revision History

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